10.11.3 PLL Feedback Divider Register
Note:
-
The allowed range is 16-200 (decimal). The rest of the values are reserved and should be avoided. The power on the default feedback divider is 150 (decimal) with an 8 MHz FRC input clock. The VCO frequency is 1.2 GHz.
Legend: r = Reserved bit
| Name: | PLLFBD |
| Offset: | 0xF8A |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Reserved[3:0] | |||||||||
| Access | r | r | r | r | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PLLFBDIV[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | |
Bits 11:8 – Reserved[3:0]
Maintain as ‘0’
Bits 7:0 – PLLFBDIV[7:0] PLL Feedback Divider bits (also denoted as ‘M’, PLL multiplier)
| Value | Description |
|---|---|
| 11111111 | Reserved |
| . . . | |
| 11001000 | 200 Maximum(1) |
| . . . | |
| 10010110 | 150 (default) |
| 00000001 | Reserved |
| 00000000 | Reserved |