11.6.10 SRAM Error Correction Code Status
Name: | ECCSTS |
Address: | 0x0101 |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | RO | RO | RO | RO | RO | RO | RO | RO | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
ERSTS[1:0] | ERRSYN[5:0] | ||||||||
Access | R/W | R/W | RC | RC | RC | RC | RC | RC | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
DBERCNT[7:0] | |||||||||
Access | RC | RC | RC | RC | RC | RC | RC | RC | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
SBERCNT[7:0] | |||||||||
Access | RC | RC | RC | RC | RC | RC | RC | RC | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 23:22 – ERSTS[1:0] Error Status
Value | Description |
---|---|
00 |
No ECC error detected |
01 |
Double bit error detected |
10 |
Overall parity error detected (correctable) |
11 |
Single bit error detected (correctable) |
Bits 21:16 – ERRSYN[5:0] Error Syndrome
When a memory error is detected, this field contains the computed syndrome value. In the case of a single bit error, this syndrome will indicate which bit (0-38) contained the error (and was corrected).
Value | Description |
---|---|
x00 |
No single bit error detected |
x01 |
SRAM bit 1, Parity bit 1 error |
x02 |
SRAM bit 2, Parity bit 2 error |
x03 |
SRAM bit 3, Data bit 0 error |
x04 |
SRAM bit 4, Parity bit 3 error |
x05 |
SRAM bit 5, Data bit 1 error |
x06 |
SRAM bit 6, Data bit 2 error |
x07 |
SRAM bit 7, Data bit 3 error |
x08 |
SRAM bit 8, Parity bit 4 error |
x09 |
SRAM bit 9, Data bit 4 error |
x0A |
SRAM bit 10, Data bit 5 error |
x0B |
SRAM bit 11, Data bit 6 error |
x0C |
SRAM bit 12, Data bit 7 error |
x0D |
SRAM bit 13, Data bit 8 error |
x0E |
SRAM bit 14, Data bit 9 error |
x0F |
SRAM bit 15, Data bit 10 error |
x10 |
SRAM bit 16, Parity bit 5 error |
x11 |
SRAM bit 17, Data bit 11 error |
x12 |
SRAM bit 18, Data bit 12 error |
x13 |
SRAM bit 19, Data bit 13 error |
x14 |
SRAM bit 20, Data bit 14 error |
x15 |
SRAM bit 21, Data bit 15 error |
x16 |
SRAM bit 22, Data bit 16 error |
x17 |
SRAM bit 23, Data bit 17 error |
x18 |
SRAM bit 24, Data bit 18 error |
x19 |
SRAM bit 25, Data bit 19 error |
x1A |
SRAM bit 26, Data bit 20 error |
x1B |
SRAM bit 27, Data bit 21 error |
x1C |
SRAM bit 28, Data bit 22 error |
x1D |
SRAM bit 29, Data bit 23 error |
x1E |
SRAM bit 30, Data bit 24 error |
x1F |
SRAM bit 31, Data bit 25 error |
x20 |
SRAM bit 32, Parity bit 6 error |
x21 |
SRAM bit 33, Data bit 26 error |
x22 |
SRAM bit 34, Data bit 27 error |
x23 |
SRAM bit 35, Data bit 28 error |
x24 |
SRAM bit 36, Data bit 29 error |
x25 |
SRAM bit 37, Data bit 30 error |
x26 |
SRAM bit 38, Data bit 31 error |
Bits 15:8 – DBERCNT[7:0] Double Bit Error Count
This field counts the number of double bit errors detected. The count will not saturate at 0xFF and will roll over to 0x00.
Bits 7:0 – SBERCNT[7:0] Single Bit Error Count
This field counts the number of single bit errors detected. The count will not saturate at the value configured in the Single Bit Error Limit (SBERLMT) and instead roll over to 0x00.