11.6.11 SRAM Error Correction Code Fault Injection Control
| Name: | ECCFLTCTRL |
| Address: | 0x0102 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| FLTINJADR[12:8] | |||||||||
| Access | RO | RO | RO | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FLTINJADR[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FLTINJONCE | FLTINJBIT2[5:0] | ||||||||
| Access | RO | R/W SC | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLTINJAEQ | FLTINJEN | FLTINJBIT1[5:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 28:16 – FLTINJADR[12:0] Fault Injection Address
only a READ from this address gets injected; Byte address, same as AHB. LSB 2 bits will be ignored.
Bit 14 – FLTINJONCE Fault Injection Once
| Value | Description |
|---|---|
0 |
Inject fault on every read of the Fault Injection Address |
1 |
Only inject the fault on the next read of the Fault Injection Address |
Bits 13:8 – FLTINJBIT2[5:0] Fault Injection Bit 2
This field configures which bit will be flipped on read of the SRAM. For single bit errors, configure this field to be the same as the Fault Injection Bit 1 (FLTINJBIT1) field. For double bit errors, configure this field to be different than the Fault Injection Bit 1 field.
| Value | Description |
|---|---|
x00 |
Inject fault into read of SRAM bit 0 |
x01 |
Inject fault into read of SRAM bit 1 |
... |
... |
x25 |
Inject fault into read of SRAM bit 37 |
x26 |
Inject fault into read of SRAM bit 38 |
x27 |
Reserved |
x28 |
Reserved |
... |
... |
x3F |
Reserved |
Bit 7 – FLTINJAEQ Fault Injection Address Equal
When set, the fault will only be injected when a SRAM read to the address specified by the Fault Injection Address field is performed.
| Value | Description |
|---|---|
0 |
|
1 |
Inject fault when SRAM address equals the Fault Injection Address field |
Bit 6 – FLTINJEN Fault Injection Enable
When this bit is set, bits will be flipped on the read of data from the SRAM address configured in the Fault Injection Address (FLTINJADR) field. The Fault Injection Address Equal (FLTINJAEQ) bit must also be set.
| Value | Description |
|---|---|
0 |
Fault injection is disabled |
1 |
Fault injection is enabled |
Bits 5:0 – FLTINJBIT1[5:0] Fault Injection Bit 1
This field configures which bit will be flipped on read of the SRAM. For single bit errors, configure this field to be the same as the Fault Injection Bit 2 (FLTINGBIT2) field. For double bit errors, configure this field to be different than the Fault Injection Bit 2 field.
| Value | Description |
|---|---|
x00 |
Inject fault into read of SRAM bit 0 |
x01 |
Inject fault into read of SRAM bit 1 |
... |
... |
x25 |
Inject fault into read of SRAM bit 37 |
x26 |
Inject fault into read of SRAM bit 38 |
x27 |
Reserved |
x28 |
Reserved |
... |
... |
x3F |
Reserved |