11.6.2 Queue Receive Configuration
Important: When updating the
fields of this register, the contents of reserved bits must not be changed. A
read-modified-write process must be used when writing to this register.
Important: Fields in this
register shall only be changed prior to setting the Configuration Synchronization
(SYNC) bit in the OPEN Alliance Configuration 0 (OA_CONFIG0) register enabling
Ethernet packet transfer. Once the SYNC bit has been set, fields in this register
must not be changed without resetting the MAC-PHY.
| Name: | QRXCFG |
| Address: | 0x0082 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| BUFSZ[2:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | RO | RO | RO | RO | |
| Reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | RO | RO | RO | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | RO | RO | |
| Reset | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
Bits 22:20 – BUFSZ[2:0] Buffer Size
Number of bytes allocated to each buffer in the receive queue.
Important: The buffer size configured in this field
must match the Block Payload Size (BPS) configured in the OPEN Alliance Configuration
0 (OA_CONFIG0) register.
| Value | Description |
|---|---|
000 |
32 Bytes |
001 |
64 Bytes (default) |
| Others | Reserved |