LAN8650/1

Description
Conformity
1 Preface
2 Introduction
3 Pin Descriptions and Assignments
4 Global Functional Descriptions
5 Serial Peripheral Interface (SPI)
6 Ethernet MAC
7 Integrated PHY
8 Application Information
9 Operational Characteristics
10 Packaging Information
11 Register Descriptions
- 11.1 Open Alliance 10BASE-T1x MAC-PHY Standard Registers
- 11.2 MAC Registers
- 11.3 PHY PCS Registers
- 11.4 PHY PMA/PMD Registers
- 11.5 PHY Vendor Specific Registers
- 11.6 Miscellaneous Register Descriptions
  - 11.6.1 Queue Transmit Configuration
    Queue Transmit Configuration
  - 11.6.2 Queue Receive Configuration
    Queue Receive Configuration
  - 11.6.3 Pad Control Register
    Pad Control Register
  - 11.6.4 Clock Output Control
    Clock Output Control
  - 11.6.5 Miscellaneous
    Miscellaneous
  - 11.6.6 Device Identification
    Device Identification
  - 11.6.7 Bus Parity Control and Status
    Bus Parity Control and Status
  - 11.6.8 Configuration Protection Control
    Configuration Protection Control
  - 11.6.9 SRAM Error Correction Code Control
    SRAM Error Correction Code Control
  - 11.6.10 SRAM Error Correction Code Status
    SRAM Error Correction Code Status
  - 11.6.11 SRAM Error Correction Code Fault Injection Control
    SRAM Error Correction Code Fault Injection Control
  - 11.6.12 Event Capture 0 Control Register
    Event Capture 0 Control Register
  - 11.6.13 Event Capture 1 Control Register
    Event Capture 1 Control Register
  - 11.6.14 Event Capture 2 Control Register
    Event Capture 2 Control Register
  - 11.6.15 Event Capture 3 Control Register
    Event Capture 3 Control Register
  - 11.6.16 Event Capture Read Status Register
    Event Capture Read Status Register
  - 11.6.17 Event Capture Total Counts Register
    Event Capture Total Counts Register
  - 11.6.18 Event Capture Clock Seconds High Register
    Event Capture Clock Seconds High Register
  - 11.6.19 Event Capture Clock Seconds Low Register
    Event Capture Clock Seconds Low Register
  - 11.6.20 Event Capture Clock Nanoseconds Register
    Event Capture Clock Nanoseconds Register
  - 11.6.21 Event Capture Read Timestamp Register n
    Event Capture Read Timestamp Register n
  - 11.6.22 Phase Adjuster Cycles Register
    Phase Adjuster Cycles Register
  - 11.6.23 Phase Adjuster Control Register
    Phase Adjuster Control Register
  - 11.6.24 Event 0 Start Time Nanoseconds Register
    Event 0 Start Time Nanoseconds Register
  - 11.6.25 Event 0 Start Time Seconds Low Register
    Event 0 Start Time Seconds Low Register
  - 11.6.26 Event 0 Start Time Seconds High Register
    Event 0 Start Time Seconds High Register
  - 11.6.27 Event 0 Pulse Width Register
    Event 0 Pulse Width Register
  - 11.6.28 Event 0 Idle Time Register
    Event 0 Idle Time Register
  - 11.6.29 Event Generator 0 Control Register
    Event Generator 0 Control Register
  - 11.6.30 Event 1 Start Time Nanoseconds Register
    Event 1 Start Time Nanoseconds Register
  - 11.6.31 Event 1 Start Time Seconds Low Register
    Event 1 Start Time Seconds Low Register
  - 11.6.32 Event 1 Start Time Seconds High Register
    Event 1 Start Time Seconds High Register
  - 11.6.33 Event 1 Pulse Width Register
    Event 1 Pulse Width Register
  - 11.6.34 Event 1 Idle Time Register
    Event 1 Idle Time Register
  - 11.6.35 Event Generator 1 Control Register
    Event Generator 1 Control Register
  - 11.6.36 Event 2 Start Time Nanoseconds Register
    Event 2 Start Time Nanoseconds Register
  - 11.6.37 Event 2 Start Time Seconds Low Register
    Event 2 Start Time Seconds Low Register
  - 11.6.38 Event 2 Start Time Seconds High Register
    Event 2 Start Time Seconds High Register
  - 11.6.39 Event 2 Pulse Width Register
    Event 2 Pulse Width Register
  - 11.6.40 Event 2 Idle Time Register
    Event 2 Idle Time Register
  - 11.6.41 Event Generator 2 Control Register
    Event Generator 2 Control Register
  - 11.6.42 Event 3 Start Time Nanoseconds Register
    Event 3 Start Time Nanoseconds Register
  - 11.6.43 Event 3 Start Time Seconds Low Register
    Event 3 Start Time Seconds Low Register
  - 11.6.44 Event 3 Start Time Seconds High Register
    Event 3 Start Time Seconds High Register
  - 11.6.45 Event 3 Pulse Width Register
    Event 3 Pulse Width Register
  - 11.6.46 Event 3 Idle Time Register
    Event 3 Idle Time Register
  - 11.6.47 Event Generator 3 Control Register
    Event Generator 3 Control Register
  - 11.6.48 One Pulse-per-Second Control Register
    One Pulse-per-Second Control Register
  - 11.6.49 Synchronization Event Interrupt Enable Register
    Synchronization Event Interrupt Enable Register
  - 11.6.50 Synchronization Event Interrupt Disable Register
    Synchronization Event Interrupt Disable Register
  - 11.6.51 Synchronization Event Interrupt Mask Status Register
    Synchronization Event Interrupt Mask Status Register
  - 11.6.52 Synchronization Event Status Register
    Synchronization Event Status Register
Data Sheet Revision History
Microchip Information

11.6.1 Queue Transmit Configuration

Important: When updating the fields of this register, the contents of reserved bits must not be changed. A read-modified-write process must be used when writing to this register.

Important: Fields in this register shall only be changed prior to setting the Configuration Synchronization (SYNC) bit in the OPEN Alliance Configuration 0 (OA_CONFIG0) register enabling Ethernet packet transfer. Once the SYNC bit has been set, fields in this register must not be changed without resetting the MAC-PHY.

Name:	QTXCFG
Address:	0x0081


Bit	31	30	29	28	27	26	25	24
	CTTHR[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	1	0	1	1	0	0	0


Bit	23	22	21	20	19	18	17	16
		BUFSZ[2:0]			MACFCSDIS
Access	R/W	R/W	R/W	R/W	R/W	RO	RO	RO
Reset	0	0	0	1	0	0	0	0


Bit	15	14	13	12	11	10	9	8

Access	RO	RO	RO	RO	RO	RO	RO	RO
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0

Access	RO	RO	RO	RO	RO	RO	RO	RO
Reset	0	0	0	0	0	0	0	0

Bits 31:30 – CTTHR[1:0] Cut-through threshold

This field configures the minimum number of buffers / blocks of Ethernet frame data to fill from the SPI host before the MAC may begin to transmit to the network in cut-through mode.

Value	Description
`00`	1 block
`01`	2 block (Default)
`10`	3 block
`11`	4 block

Bits 22:20 – BUFSZ[2:0] Buffer Size

Number of bytes allocated to each buffer in the transmit queue.

Important: The buffer size configured in this field must match the Block Payload Size (BPS) configured in the OPEN Alliance Configuration 0 (OA_CONFIG0) register.

Value	Description
`000`	32 Bytes
`001`	64 Bytes (default)
Others	Reserved

Bit 19 – MACFCSDIS MAC Frame Check Sequence Disable

By default, the device will accept transmit frames from the SPI host and the MAC will automatically pad the frames to the minimum 64 byte length with an appended calculated Frame Check Sequence (FCS). When set, this bit will disable the automatic padding and FCS insertion into transmitted frames, assuming that the SPI host has already performed padding and appending of the FCS. Additionally, when this bit is set, the MACPHY will validate the FCS of the frame received from the SPI host. If the FCS does not match, indicating a possible bit-error over the SPI link, the frame will not be transmitted to the network.

Value	Description
`0`	MAC will perform frame padding and insertion of the FCS
`1`	The MAC will not pad the frame or insert the FCS. The SPI host is responsible for padding the frame to the minimum size and appending the FCS.

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