11.6.1 Queue Transmit Configuration

Important: When updating the fields of this register, the contents of reserved bits must not be changed. A read-modified-write process must be used when writing to this register.
Important: Fields in this register shall only be changed prior to setting the Configuration Synchronization (SYNC) bit in the OPEN Alliance Configuration 0 (OA_CONFIG0) register enabling Ethernet packet transfer. Once the SYNC bit has been set, fields in this register must not be changed without resetting the MAC-PHY.
Name: QTXCFG
Address: 0x0081

Bit 3130292827262524 
 CTTHR[1:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 01011000 
Bit 2322212019181716 
 BUFSZ[2:0]MACFCSDIS 
Access R/WR/WR/WR/WR/WRORORO 
Reset 00010000 
Bit 15141312111098 
  
Access RORORORORORORORO 
Reset 00000000 
Bit 76543210 
  
Access RORORORORORORORO 
Reset 00000000 

Bits 31:30 – CTTHR[1:0] Cut-through threshold

This field configures the minimum number of buffers / blocks of Ethernet frame data to fill from the SPI host before the MAC may begin to transmit to the network in cut-through mode.

ValueDescription
00 1 block
01 2 block (Default)
10 3 block
11 4 block

Bits 22:20 – BUFSZ[2:0] Buffer Size

Number of bytes allocated to each buffer in the transmit queue.

Important: The buffer size configured in this field must match the Block Payload Size (BPS) configured in the OPEN Alliance Configuration 0 (OA_CONFIG0) register.
ValueDescription
000 32 Bytes
001 64 Bytes (default)
Others Reserved

Bit 19 – MACFCSDIS MAC Frame Check Sequence Disable

By default, the device will accept transmit frames from the SPI host and the MAC will automatically pad the frames to the minimum 64 byte length with an appended calculated Frame Check Sequence (FCS). When set, this bit will disable the automatic padding and FCS insertion into transmitted frames, assuming that the SPI host has already performed padding and appending of the FCS. Additionally, when this bit is set, the MACPHY will validate the FCS of the frame received from the SPI host. If the FCS does not match, indicating a possible bit-error over the SPI link, the frame will not be transmitted to the network.

ValueDescription
0 MAC will perform frame padding and insertion of the FCS
1 The MAC will not pad the frame or insert the FCS. The SPI host is responsible for padding the frame to the minimum size and appending the FCS.