11.6.52 Synchronization Event Status Register

This register indicates all event status bits set since this register was last read.
Important: All bits are cleared upon read.
Name: SEVSTS
Address: 0x023D

Bit 3130292827262524 
 PADONEPPSDONEPAER      
Access RCRCRC 
Reset 000 
Bit 2322212019181716 
     EG3DONEEG2DONEEG1DONEEG0DONE 
Access RCRCRCRC 
Reset 0000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
 EC3DAEC3OFEC2DAEC2OFEC1DAEC1OFEC0DAEC0OF 
Access RCRCRCRCRCRCRCRC 
Reset 00000000 

Bit 31 – PADONE Phase Adjust done

This bit is set to indicate that phase adjust has completed. This bit will be cleared on read.

Bit 30 – PPSDONE One pulse-per-second signal generation done

This bit is set to indicate that the pulse per second signal generation has completed. This bit will be cleared on read.

Bit 29 – PAER Phase adjust error

This bit is set to indicate that an error was detected by the phase adjuster. This bit will be cleared on read.

Bit 19 – EG3DONE Event generator 3 done

This bit is set to indicate when event generator 3 has completed generation of a pulse or pulse sequence. This bit will be cleared on read.

Bit 18 – EG2DONE Event generator 2 done

This bit is set to indicate when event generator 2 has completed generation of a pulse or pulse sequence. This bit will be cleared on read.

Bit 17 – EG1DONE Event generator 1 done

This bit is set to indicate when event generator 1 has completed generation of a pulse or pulse sequence. This bit will be cleared on read.

Bit 16 – EG0DONE Event generator 0 done

This bit is set to indicate when event generator 0 has completed generation of a pulse or pulse sequence. This bit will be cleared on read.

Bit 7 – EC3DA Event capture unit 3 data available

This bit is set to indicate that timestamps are available to be read from event capture unit 3. This bit will be cleared on read.

Bit 6 – EC3OF Event capture unit 3 overflow

This bit is set to indicate that event capture unit 3 has failed to capture a timestamp because no more storage was available. This bit will be cleared on read.

Bit 5 – EC2DA Event capture unit 2 data available

This bit is set to indicate that timestamps are available to be read from event capture unit 2. This bit will be cleared on read.

Bit 4 – EC2OF Event capture unit 2 overflow

This bit is set to indicate that event capture unit 2 has failed to capture a timestamp because no more storage was available. This bit will be cleared on read.

Bit 3 – EC1DA Event capture unit 1 data available

This bit is set to indicate that timestamps are available to be read from event capture unit 1. This bit will be cleared on read.

Bit 2 – EC1OF Event capture unit 1 overflow

This bit is set to indicate that event capture unit 1 has failed to capture a timestamp because no more storage was available. This bit will be cleared on read.

Bit 1 – EC0DA Event capture unit 0 data available

This bit is set to indicate that timestamps are available to be read from event capture unit 0. This bit will be cleared on read.

Bit 0 – EC0OF Event capture unit 0 overflow

This bit is set to indicate that event capture unit 0 has failed to capture a timestamp because no more storage was available. This bit will be cleared on read.