11.6.9 SRAM Error Correction Code Control

Name: ECCCTRL
Address: 0x0100

Bit 3130292827262524 
  
Access RORORORORORORORO 
Reset 00000000 
Bit 2322212019181716 
 DECDISENCDIS 
Access ROROROROROR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 SBERLMT[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00100000 
Bit 76543210 
 ERONESHTERCLRBERCNTEN 
Access ROROROROROR/WR/W1 SCR/W 
Reset 00000000 

Bit 17 – DECDIS ECC Decoder Disable

When set, this bit will disable the ECC decoder.

ValueDescription
0 ECC decoder enabled
1 ECC decoder disabled

Bit 16 – ENCDIS ECC Encoder Disable

When set, this bit will disable the ECC encoder.

ValueDescription
0 ECC encoder enabled
1 ECC encoder disabled

Bits 15:8 – SBERLMT[7:0] Single Bit Error Limit

This field configures the limit for detected single bit errors.

Bit 2 – ERONESHT Error One Shot

This bit configures how errors are captured. When set, only the first error status and syndrome will be captured. When cleared, the latest error status and syndrome will be captured.

ValueDescription
0 Latest error/syndrome captured
1 First error/syndrome captured

Bit 1 – ERCLR Error Clear

Setting this bit will cause the ECC status register to clear.

Note: When set, the hardware will clear this bit automatically.
ValueDescription
0 Normal operation
1 Clear ECC status register

Bit 0 – BERCNTEN Bit Error Count Enable

When set, this bit will enable the error counters (single-bit, double-bit, etc.). When clear, the counters are frozen, but not cleared.

ValueDescription
0 Bit error counters are frozen
1 Bit error counters are enabled