11.6.9 SRAM Error Correction Code Control
Name: | ECCCTRL |
Address: | 0x0100 |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | RO | RO | RO | RO | RO | RO | RO | RO | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
DECDIS | ENCDIS | ||||||||
Access | RO | RO | RO | RO | RO | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
SBERLMT[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
ERONESHT | ERCLR | BERCNTEN | |||||||
Access | RO | RO | RO | RO | RO | R/W | R/W1 SC | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 17 – DECDIS ECC Decoder Disable
When set, this bit will disable the ECC decoder.
Value | Description |
---|---|
0 |
ECC decoder enabled |
1 |
ECC decoder disabled |
Bit 16 – ENCDIS ECC Encoder Disable
When set, this bit will disable the ECC encoder.
Value | Description |
---|---|
0 |
ECC encoder enabled |
1 |
ECC encoder disabled |
Bits 15:8 – SBERLMT[7:0] Single Bit Error Limit
This field configures the limit for detected single bit errors.
Bit 2 – ERONESHT Error One Shot
This bit configures how errors are captured. When set, only the first error status and syndrome will be captured. When cleared, the latest error status and syndrome will be captured.
Value | Description |
---|---|
0 |
Latest error/syndrome captured |
1 |
First error/syndrome captured |
Bit 1 – ERCLR Error Clear
Setting this bit will cause the ECC status register to clear.
Note: When set, the hardware will clear this bit
automatically.
Value | Description |
---|---|
0 |
Normal operation |
1 |
Clear ECC status register |
Bit 0 – BERCNTEN Bit Error Count Enable
When set, this bit will enable the error counters (single-bit, double-bit, etc.). When clear, the counters are frozen, but not cleared.
Value | Description |
---|---|
0 |
Bit error counters are frozen |
1 |
Bit error counters are enabled |