11.6.3 Pad Control Register

Name:	PADCTRL
Address:	x0088


Bit	31	30	29	28	27	26	25	24
	PDRV3[1:0]		PDRV2[1:0]		PDRV1[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	1	1	1	1	1	-	-


Bit	23	22	21	20	19	18	17	16
	REFCLKSEL						ACMASEL[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	-	-	-	-	0	0	0


Bit	15	14	13	12	11	10	9	8
					B0SEL[1:0]		A4SEL[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	-	-	0	0	0	1	0	0


Bit	7	6	5	4	3	2	1	0
	A3SEL[1:0]		A2SEL[1:0]		A1SEL[1:0]		A0SEL[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:30 – PDRV3[1:0] Digital Output Pad Drive Strength

This field configures the output pad drive strength for pin group 3.

Value	Description
`00`	Low current drive
`01`	Medium-low current drive
`10`	Medium-high current drive
`11`	High current drive (default)

Bits 29:28 – PDRV2[1:0] Digital Output Pad Drive Strength

This field configures the output pad drive strength for pin group 2.

Value	Description
`00`	Low current drive
`01`	Medium-low current drive
`10`	Medium-high current drive
`11`	High current drive (default)

Bits 27:26 – PDRV1[1:0] Digital Output Pad Drive Strength

This field configures the output pad drive strength for pin group 1.

Value	Description
`00`	Low current drive
`01`	Medium-low current drive
`10`	Medium-high current drive
`11`	High current drive (default)

Bit 23 – REFCLKSEL Reference Clock Select

This bit selects the clock reference clock used for event capture, event generation and time stamping.

Value	Description
`0`	Reference clock is the internal 25 MHz clock derived from attached crystal.
`1`	Reference clock is an external clock on pin DIOB0. The DIOB0 Select (B0SEL) bit field below must also be configured to 00b (external reference clock input).

Bits 17:16 – ACMASEL[1:0] ACMA Input Select

Selects the ACMA input pin.

Value	Description
`00`	ACMA disabled
`01`	ACMA enabled with the control signal provided by event generator 0 Note: If this value is selected, event generator 0 cannot be used as a DIO pin source.
`10`	ACMA enabled with the control signal on DIOA2
`11`	Reserved

Bits 11:10 – B0SEL[1:0] DIOB0 Signal Select

This field configures the DIOB0 pin signal select.

Note: The DIOB0 pin is configured by default to be an output.

Value	Description
`00`	External 1588 reference clock (requires configuration in REFCLKSEL bit field above) (Input)
`01`	Clock output as configured in Clock Output Control Register, CLKOEN (Output) If this pin is not used, it may be connected to ground as long as the clock output is disabled in CLKOEN.
`10`	Reserved (Input)
`11`	Reserved (Input)

Bits 9:8 – A4SEL[1:0] DIOA4 Signal Select

This field configures the DIOA4 pin signal select

Value	Description
`00`	Reserved (Input)
`01`	1PPS (Output)
`10`	Event Generator 2 (Output) Note: No signal will be provided to DIOA4 if ACMASEL = 2.
`11`	Event Generator 3 (Output)

Bits 7:6 – A3SEL[1:0] DIOA3 Signal Select

This field configures the DIOA3 pin signal select

Value	Description
`00`	Event Capture (Input)
`01`	Event Generator 3 (Output)
`10`	Reserved (Output)
`11`	Reserved (Output)

Bits 5:4 – A2SEL[1:0] DIOA2 Signal Select

This field configures the DIOA2 pin signal select

Value	Description
`00`	ACMA and/or Event Capture (Input) ACMA is configured in the ACMASEL bits, above
`01`	Event Generator 2 (Output) Note: No signal will be provided to DIOA2 if ACMASEL = 2.
`10`	Reserved (Output)
`11`	Reserved (Input)

Bits 3:2 – A1SEL[1:0] DIOA1 Signal Select

This field configures the DIOA1 pin signal select

Value	Description
`00`	Event Capture (Input)
`01`	Event Generator 1 (Output)
`10`	Reserved (Output)
`11`	Reserved (Output)

Bits 1:0 – A0SEL[1:0] DIOA0 Signal Select

This field configures the DIOA0 pin signal select

Value	Description
`00`	Event Capture (Input)
`01`	Event Generator 0 (Output)
`10`	Reserved (Output)
`11`	Reserved (Output)

LAN8650/1