11.6.50 Synchronization Event
Interrupt Disable Register
Note: The bits of this register are W1S.
Name: | SEVINTDIS |
Address: | 0x023B |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PADONE | PPSDONE | | | | | | | |
Access | W1S | W1S | | | | | | | |
Reset | 0 | 0 | | | | | | | |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | EG3DONE | EG2DONE | EG1DONE | EG0DONE | |
Access | | | | | W1S | W1S | W1S | W1S | |
Reset | | | | | 0 | 0 | 0 | 0 | |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | | | | |
Access | | | | | | | | | |
Reset | | | | | | | | | |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EC3DA | EC3OF | EC2DA | EC2OF | EC1DA | EC1OF | EC0DA | EC0OF | |
Access | W1S | W1S | W1S | W1S | W1S | W1S | W1S | W1S | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – PADONE Phase Adjust
Done
Setting this bit
will prevent any effect on the SEV bit of OA_STATUS1 when phase adjust is
done.
Bit 30 – PPSDONE One
pulse-per-second signal generation done
Setting this bit will prevent
any effect on the SEV bit of OA_STATUS1 when one pulse-per-second signal generation
has completed.
Bit 30 – PAER Phase adjust
error
Setting this bit will prevent
any effect on the SEV bit of OA_STATUS1 when an error was detected by the phase
adjuster.
Bit 19 – EG3DONE Event generator 3
done
Setting this bit will prevent
any effect on the SEV bit of OA_STATUS1 when the pulse sequence configured on event
generator 3 is done.
Bit 18 – EG2DONE Event generator 2
done
Setting this bit will prevent
any effect on the SEV bit of OA_STATUS1 when the pulse sequence configured on event
generator 2 is done.
Bit 17 – EG1DONE Event generator 1
done
Setting this bit will prevent
any effect on the SEV bit of OA_STATUS1 when the pulse sequence configured on event
generator 1 is done.
Bit 16 – EG0DONE Event generator 0
done
Setting this bit will prevent
any effect on the SEV bit of OA_STATUS1 when the pulse sequence configured on event
generator 0 is done.
Bit 7 – EC3DA Event capture unit
3 data available
Setting this bit will prevent
any effect on the SEV bit of OA_STATUS1 when timestamps are available to be read
from event capture unit 3.
Bit 6 – EC3OF Event capture unit
3 overflow
Setting this bit will prevent
any effect on the SEV bit of OA_STATUS1 when event capture unit 3 has failed to
capture a timestamp because no more storage was available.
Bit 5 – EC2DA Event capture unit
2 data available.
Setting this bit will prevent
any effect on the SEV bit of OA_STATUS1 when timestamps are available to be read
from event capture unit 2.
Bit 4 – EC2OF Event capture unit
2 overflow
Setting this bit will prevent
any effect on the SEV bit of OA_STATUS1 when event capture unit 2 has failed to
capture a timestamp because no more storage was available.
Bit 3 – EC1DA Event capture unit
1 data available
Setting this bit will prevent
any effect on the SEV bit of OA_STATUS1when timestamps are available to be read from
event capture unit 2.
Bit 2 – EC1OF Event capture unit
1 overflow
Setting this bit will prevent
any effect on the SEV bit of OA_STATUS1 when event capture unit 1 has failed to
capture a timestamp because no more storage was available.
Bit 1 – EC0DA Event capture unit
0 data available
Setting this bit will prevent
any effect on the SEV bit of OA_STATUS1 when timestamps are available to be read
from event capture unit 0.
Bit 0 – EC0OF Event capture unit
0 overflow
Setting this bit will prevent
any effect on the SEV bit of OA_STATUS1 when event capture unit 0 has failed to
capture a timestamp because no more storage was available.