11.6.7 Bus Parity Control and Status
| Name: | BUSPCS |
| Address: | 0x96 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | RO | RO | RO | RO | RO | RO | RO | RO | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| MBMPER | SPIPER | CSRBPER | SRAMPER | ||||||
| Access | RO | RO | RO | RO | RC | RC | RC | RC | |
| Reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | RO | RO | RO | RO | RO | RO | RO | RO | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CSRBDPERG | SRAMDPERI | MBMDPERI | BMGRAPERI | PARGCEN | |||||
| Access | RO | RO | RO | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
Bit 19 – MBMPER MAC Buffer Manager Parity Error Status
This bit is set when the MAC buffer manager detects a bus parity error.
| Value | Description |
|---|---|
0 |
No bus parity error detected |
1 |
Bus parity error has been detected by MAC buffer manager |
Bit 18 – SPIPER SPI Parity Error Status
This bit is set when the SPI block detects a bus parity error.
| Value | Description |
|---|---|
0 |
No bus parity error detected |
1 |
Bus parity error has been detected by SPI block |
Bit 17 – CSRBPER Control/Status Register Bridge Parity Error Status
This bit is set when the bridge to the control/status registers detects a bus parity error. If the parity error occurs during a read operation, the bridge will return a data value of zero. Write operations to the control/status register bridge will be blocked on detection of a parity error.
| Value | Description |
|---|---|
0 |
No bus parity error detected |
1 |
Bus parity error has been detected by the control/status register bridge |
Bit 16 – SRAMPER SRAM Controller Parity Error Status
This bit is set when the SRAM controller detects a bus parity error. If the parity occurs on a read from the SRAM, the controller will return data of zero. Write operations to the SRAM will be blocked on detection of a parity error.
| Value | Description |
|---|---|
0 |
No bus parity error detected |
1 |
Bus parity error has been detected by the SRAM controller |
Bit 4 – CSRBDPERG Bridge Parity Error Injection
When this bit is set, the bridge to the control/status register bus will inject a bus data parity error on read.
| Value | Description |
|---|---|
0 |
Normal operation |
1 |
Control/status register bridge will inject a data read parity error onto the bus |
Bit 3 – SRAMDPERI SRAM Controller Parity Error Injection
When this bit is set, the SRAM controller will inject a bus data parity error on read.
| Value | Description |
|---|---|
0 |
Normal operation |
1 |
SRAM controller will inject a bus data read parity error onto the bus |
Bit 2 – MBMDPERI Buffer Manager Data Parity Error Injection
When this bit is set, the MAC buffer manager will inject a bus data parity error on write.
| Value | Description |
|---|---|
0 |
Normal operation |
1 |
MAC buffer manager will inject a data parity error on write bus accesses |
Bit 1 – BMGRAPERI Buffer Manager Address Parity Error Injection
When this bit is set, the BMAC buffer manager will inject a bus address parity error on read and write.
| Value | Description |
|---|---|
0 |
Normal operation |
1 |
MAC buffer manager will inject an address parity error on read/write bus accesses |
Bit 0 – PARGCEN Parity Generation and Check Enable
When set, this bit will enable the parity generation and checking on the internal bus.
| Value | Description |
|---|---|
0 |
Internal bus parity generation and checking is disabled (default) |
1 |
Internal bus parity generation and checking is enabled |