11.6.22 Phase Adjuster Cycles Register

Name: PACYC
Address: 0x021F

Bit 3130292827262524 
 CYC[29:24] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 CYC[23:16] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 CYC[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 CYC[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 29:0 – CYC[29:0]

ValueDescription
0 - 0x3FFF_FFFF Number of clock cycles between phase adjustments.