LAN8650/1

Description
Conformity
1 Preface
2 Introduction
3 Pin Descriptions and Assignments
4 Global Functional Descriptions
5 Serial Peripheral Interface (SPI)
6 Ethernet MAC
7 Integrated PHY
8 Application Information
9 Operational Characteristics
10 Packaging Information
11 Register Descriptions
- 11.1 Open Alliance 10BASE-T1x MAC-PHY Standard Registers
- 11.2 MAC Registers
- 11.3 PHY PCS Registers
- 11.4 PHY PMA/PMD Registers
- 11.5 PHY Vendor Specific Registers
- 11.6 Miscellaneous Register Descriptions
  - 11.6.1 Queue Transmit Configuration
    Queue Transmit Configuration
  - 11.6.2 Queue Receive Configuration
    Queue Receive Configuration
  - 11.6.3 Pad Control Register
    Pad Control Register
  - 11.6.4 Clock Output Control
    Clock Output Control
  - 11.6.5 Miscellaneous
    Miscellaneous
  - 11.6.6 Device Identification
    Device Identification
  - 11.6.7 Bus Parity Control and Status
    Bus Parity Control and Status
  - 11.6.8 Configuration Protection Control
    Configuration Protection Control
  - 11.6.9 SRAM Error Correction Code Control
    SRAM Error Correction Code Control
  - 11.6.10 SRAM Error Correction Code Status
    SRAM Error Correction Code Status
  - 11.6.11 SRAM Error Correction Code Fault Injection Control
    SRAM Error Correction Code Fault Injection Control
  - 11.6.12 Event Capture 0 Control Register
    Event Capture 0 Control Register
  - 11.6.13 Event Capture 1 Control Register
    Event Capture 1 Control Register
  - 11.6.14 Event Capture 2 Control Register
    Event Capture 2 Control Register
  - 11.6.15 Event Capture 3 Control Register
    Event Capture 3 Control Register
  - 11.6.16 Event Capture Read Status Register
    Event Capture Read Status Register
  - 11.6.17 Event Capture Total Counts Register
    Event Capture Total Counts Register
  - 11.6.18 Event Capture Clock Seconds High Register
    Event Capture Clock Seconds High Register
  - 11.6.19 Event Capture Clock Seconds Low Register
    Event Capture Clock Seconds Low Register
  - 11.6.20 Event Capture Clock Nanoseconds Register
    Event Capture Clock Nanoseconds Register
  - 11.6.21 Event Capture Read Timestamp Register n
    Event Capture Read Timestamp Register n
  - 11.6.22 Phase Adjuster Cycles Register
    Phase Adjuster Cycles Register
  - 11.6.23 Phase Adjuster Control Register
    Phase Adjuster Control Register
  - 11.6.24 Event 0 Start Time Nanoseconds Register
    Event 0 Start Time Nanoseconds Register
  - 11.6.25 Event 0 Start Time Seconds Low Register
    Event 0 Start Time Seconds Low Register
  - 11.6.26 Event 0 Start Time Seconds High Register
    Event 0 Start Time Seconds High Register
  - 11.6.27 Event 0 Pulse Width Register
    Event 0 Pulse Width Register
  - 11.6.28 Event 0 Idle Time Register
    Event 0 Idle Time Register
  - 11.6.29 Event Generator 0 Control Register
    Event Generator 0 Control Register
  - 11.6.30 Event 1 Start Time Nanoseconds Register
    Event 1 Start Time Nanoseconds Register
  - 11.6.31 Event 1 Start Time Seconds Low Register
    Event 1 Start Time Seconds Low Register
  - 11.6.32 Event 1 Start Time Seconds High Register
    Event 1 Start Time Seconds High Register
  - 11.6.33 Event 1 Pulse Width Register
    Event 1 Pulse Width Register
  - 11.6.34 Event 1 Idle Time Register
    Event 1 Idle Time Register
  - 11.6.35 Event Generator 1 Control Register
    Event Generator 1 Control Register
  - 11.6.36 Event 2 Start Time Nanoseconds Register
    Event 2 Start Time Nanoseconds Register
  - 11.6.37 Event 2 Start Time Seconds Low Register
    Event 2 Start Time Seconds Low Register
  - 11.6.38 Event 2 Start Time Seconds High Register
    Event 2 Start Time Seconds High Register
  - 11.6.39 Event 2 Pulse Width Register
    Event 2 Pulse Width Register
  - 11.6.40 Event 2 Idle Time Register
    Event 2 Idle Time Register
  - 11.6.41 Event Generator 2 Control Register
    Event Generator 2 Control Register
  - 11.6.42 Event 3 Start Time Nanoseconds Register
    Event 3 Start Time Nanoseconds Register
  - 11.6.43 Event 3 Start Time Seconds Low Register
    Event 3 Start Time Seconds Low Register
  - 11.6.44 Event 3 Start Time Seconds High Register
    Event 3 Start Time Seconds High Register
  - 11.6.45 Event 3 Pulse Width Register
    Event 3 Pulse Width Register
  - 11.6.46 Event 3 Idle Time Register
    Event 3 Idle Time Register
  - 11.6.47 Event Generator 3 Control Register
    Event Generator 3 Control Register
  - 11.6.48 One Pulse-per-Second Control Register
    One Pulse-per-Second Control Register
  - 11.6.49 Synchronization Event Interrupt Enable Register
    Synchronization Event Interrupt Enable Register
  - 11.6.50 Synchronization Event Interrupt Disable Register
    Synchronization Event Interrupt Disable Register
  - 11.6.51 Synchronization Event Interrupt Mask Status Register
    Synchronization Event Interrupt Mask Status Register
  - 11.6.52 Synchronization Event Status Register
    Synchronization Event Status Register
Data Sheet Revision History
Microchip Information

11.6.51 Synchronization Event Interrupt Mask Status Register

Note: This register is read only.

Name:	SEVIM
Address:	0x023C


Bit	31	30	29	28	27	26	25	24
	PADONE	PPSDONE
Access	RO	RO
Reset	0	0


Bit	23	22	21	20	19	18	17	16
					EG3DONE	EG2DONE	EG1DONE	EG0DONE
Access					RO	RO	RO	RO
Reset					0	0	0	0


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	EC3DA	EC3OF	EC2DA	EC2OF	EC1DA	EC1OF	EC0DA	EC0OF
Access	RO	RO	RO	RO	RO	RO	RO	RO
Reset	0	0	0	0	0	0	0	0

Bit 31 – PADONE Phase Adjust Done

Value	Description
`0`	When the PADONE bit of the SEVSTS is set, the SEV bit of the OA_STATUS1 register will be set.
`1`	The PADONE bit of the SEVSTS has no effect on the OA_STATUS1 register.

Bit 30 – PPSDONE One pulse-per-second signal generation done

Value	Description
`0`	When the PPSDONE bit of the SEVSTS is set, the SEV bit of the OA_STATUS1 register will be set.
`1`	The PPSDONE bit of the SEVSTS has no effect on the OA_STATUS1 register.

Bit 30 – PAER Phase adjust error

Value	Description
`0`	When the PAER bit of the SEVSTS is set, the SEV bit of the OA_STATUS1 register will be set.
`1`	The PAER bit of the SEVSTS has no effect on the OA_STATUS1 register.

Bit 19 – EG3DONE Event generator 3 done

Value	Description
`0`	When the EG3DONE bit of the SEVSTS is set, the SEV bit of the OA_STATUS1 register will be set.
`1`	The EG3DONE bit of the SEVSTS has no effect on the OA_STATUS1 register.

Bit 18 – EG2DONE Event generator 2 done

Value	Description
`0`	When the EG2DONE bit of the SEVSTS is set, the SEV bit of the OA_STATUS1 register will be set.
`1`	The EG2DONE bit of the SEVSTS has no effect on the OA_STATUS1 register.

Bit 17 – EG1DONE Event generator 1 done

Value	Description
`0`	When the EG1DONE bit of the SEVSTS is set, the SEV bit of the OA_STATUS1 register will be set.
`1`	The EG1DONE bit of the SEVSTS has no effect on the OA_STATUS1 register.

Bit 16 – EG0DONE Event generator 0 done

Value	Description
`0`	When the EG0DONE bit of the SEVSTS is set, the SEV bit of the OA_STATUS1 register will be set.
`1`	The EG0DONE bit of the SEVSTS has no effect on the OA_STATUS1 register.

Bit 7 – EC3DA Event capture unit 3 data available

Value	Description
`0`	When the EC3DA bit of the SEVSTS is set, the SEV bit of the OA_STATUS1 register will be set.
`1`	The EC3DA bit of the SEVSTS has no effect on the OA_STATUS1 register.

Bit 6 – EC3OF Event capture unit 3 overflow

Value	Description
`0`	When the EC3OF bit of the SEVSTS is set, the SEV bit of the OA_STATUS1 register will be set.
`1`	The EC3OF bit of the SEVSTS has no effect on the OA_STATUS1 register.

Bit 5 – EC2DA Event capture unit 2 data available

Value	Description
`0`	When the EC2DA bit of the SEVSTS is set, the SEV bit of the OA_STATUS1 register will be set.
`1`	The EC2DA bit of the SEVSTS has no effect on the OA_STATUS1 register.

Bit 4 – EC2OF Event capture unit 2 overflow

T

Value	Description
`0`	When the EC2OF bit of the SEVSTS is set, the SEV bit of the OA_STATUS1 register will be set.
`1`	The EC2OF bit of the SEVSTS has no effect on the OA_STATUS1 register.

Bit 3 – EC1DA Event capture unit 1 data available

Value	Description
`0`	When the EC1DA bit of the SEVSTS is set, the SEV bit of the OA_STATUS1 register will be set.
`1`	The EC1DA bit of the SEVSTS has no effect on the OA_STATUS1 register.

Bit 2 – EC1OF Event capture unit 1 overflow

Value	Description
`0`	When the EC1OF bit of the SEVSTS is set, the SEV bit of the OA_STATUS1 register will be set.
`1`	The EC1OF bit of the SEVSTS has no effect on the OA_STATUS1 register.

Bit 1 – EC0DA Event capture unit 0 data available

Value	Description
`0`	When the EC0DA bit of the SEVSTS is set, the SEV bit of the OA_STATUS1 register will be set.
`1`	The EC0DA bit of the SEVSTS has no effect on the OA_STATUS1 register.

Bit 0 – EC0OF Event capture unit 0 overflow

Value	Description
`0`	When the EC0OF bit of the SEVSTS is set, the SEV bit of the OA_STATUS1 register will be set.
`1`	The EC0OF bit of the SEVSTS has no effect on the OA_STATUS1 register.

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