47.6.1 Control A Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLA |
| Offset: | 0x0000 |
| Reset: | 0x00000000 |
| Property: | Write-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PRIV | ENABLE | SWRST | |||||||
| Access | R/W | R/W | R/S/HC | ||||||
| Reset | 0 | 0 | 0 |
Bit 2 – PRIV Privileged Access Only
| Value | Description |
|---|---|
| 0x0 | PUF registers accessible in privileged and unprivileged modes. |
| 0x1 | PUF registers only accessible in privileged mode. |
Bit 1 – ENABLE Clock Enable Bit
| Value | Description |
|---|---|
| 0x0 | HSM clock is not requested and macros is disabled. |
| 0x1 | HSM clock is requested and macro is enabled. |
Bit 0 – SWRST Software Reset
Write ‘1’ to reset the registers and internal state. Writing a ‘0’ has no effect. SWRST stays high until the reset completes.
Note: Reset to PUF must be held active long enough to reset the complete
macro.
| Value | Description |
|---|---|
| 0x0 | No effect |
| 0x1 | Reset registers and internal state |