47.6.14 QuiddiKey Interrupt Status Register

Table 47-14. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: QK ISR
Offset: 0x218
Reset: 0x00000000
Property: R/W

The Interrupt Status register indicates which interrupt has occurred. Multiple interrupts may occur at the same time (e.g. the busy interrupt occurs together with one of the ok and error interrupts).Writing 1 to a bit, clears the corresponding bit.

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
  QK INT DO REQUESTQK INT DI REQUESTQK INT REJECTEDQK INT ZEROIZEDQK INT ERRORQK INT OKQK INT BUSY 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bit 6 – QK INT DO REQUEST QuiddiKey Data Out Interrupt

A positive edge has occurred on qk_do_request, which means that a data out transfer is requested via the QK_DOR register.

Bit 5 – QK INT DI REQUEST QuiddiKey Data In Interrupt

A positive edge has occurred on qk_di_request, which means that a data in transfer is requested via the QK_DIR register.

Bit 4 – QK INT REJECTED QuiddiKey Rejected Interrupt

A positive edge has occurred on qk_rejected, which means that a command was rejected.

Bit 3 – QK INT ZEROIZED QuiddiKey Zeroized Interrupt

A positive edge has occurred on qk_zeroized, which means that QuiddiKey has moved to the Zeroized or Locked state.

Bit 2 – QK INT ERROR QuiddiKey Error Interrupt

A positive edge has occurred on qk_error, which means that an operation has failed.

Bit 1 – QK INT OK QuiddiKey OK Interrupt

A positive edge has occurred on qk_ok, which means that an operation successfully completed.

Bit 0 – QK INT BUSY QuiddiKey Busy Interrupt

A negative edge has occurred on qk_busy, which means that an operation has completed.