47.6.19 QuiddiKey Data Output
Register
Table 47-19. Register Bit Attribute Legend| Symbol | Description | Symbol | Description | Symbol | Description |
|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | QK DOR |
| Offset: | 0x2A8 |
| Reset: | 0x00000000 |
| Property: | R |
The Data Output
register is used to transfer data from QuiddiKey. It can only be read when input data is
available (indicated by the qk_do_request signal). When read at any other moment, or
when written, an error response is generated. Depending on the way the system is
configured and connected, this may generate an exception.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | QK DO[31:24] | |
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | QK DO[23:16] | |
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | QK DO[15:8] | |
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | QK DO[7:0] | |
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:0 – QK DO[31:0] QuiddiKey Data
Output
Output data from
QuiddiKey
