47.6.13 QuiddiKey Interrupt Mask Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | QK IMR |
| Offset: | 0x214 |
| Reset: | 0x00000000 |
| Property: | R/W |
Individual QuiddiKey interrupts can be enabled or disabled with the Interrupt Mask register.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| QK INT EN DO REQUEST | QK INT EN DI REQUEST | QK INT EN REJECTED | QK INT EN ZEROIZED | QK INT EN ERROR | QK INT EN OK | QK INT EN BUSY | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 6 – QK INT EN DO REQUEST QuiddiKey Data Out Interrupt Enable
Bit 5 – QK INT EN DI REQUEST QuiddiKey Data In Interrupt Enable
Bit 4 – QK INT EN REJECTED QuiddiKey Rejected Interrupt Enable
Enables the rejected interrupt.
Bit 3 – QK INT EN ZEROIZED QuiddiKey Zeroized Interrupt Enable
Enables the zeroized interrupt.
Bit 2 – QK INT EN ERROR QuiddiKey Error Interrupt Enable
Enables the error interrupt.
Bit 1 – QK INT EN OK QuiddiKey OK Interrupt Enable
Enables the OK interrupt.
Bit 0 – QK INT EN BUSY QuiddiKey Busy Interrupt Enable
Enables the busy interrupt.