3.3.14.5 Address Register Dependencies

These are instructions subjected to a stall due to a data address dependency between the X data space read and write operations. An additional cycle is inserted to resolve the resource conflict, as discussed in Figure 3-17.

Figure 3-17. MAC-Class One-Cycle Instruction Flow

Note: DSP status cannot be updated prior to the end of the W-stage (i.e., one cycle later than the ALU status).