3.3.12.2 Multiplier

The dsPIC33A devices feature a 33-bit-by-33-bit multiplier shared by both the MCU ALU and the DSP engine. The multiplier is capable of a signed, unsigned or mixed-sign operation and supports either 9.31 fractional (Q.31) or 64-bit integer results.

The multiplier takes in 32-bit input data and converts the data to 33 bits. Signed operands to the multiplier are sign-extended. Unsigned input operands are zero-extended. The internal 33-bit representation of data in the multiplier allows correct execution of mixed-sign and unsigned 32-bit by 32-bit multiplication operations.

The representation of data in hardware for Integer and Fractional Multiplier modes is as follows:

  • Integer data is inherently represented as a signed two’s complement value, where the Most Significant bit (MSb) is defined as a Sign bit. Generally speaking, the range of an N-bit two’s complement integer is -2(N-1) to 2(N-1)-1.
  • Fractional data is represented as a two’s complement fraction, where the MSb is defined as a Sign bit, and the radix point is implied to lie just after the Sign bit (Q.X format). The range of an N-bit two’s complement fraction with this implied radix point is -1.0 to (1 – 2(1-N)).

The range of data in both Integer and Fractional modes is listed in Table 3-3. Figure 3-10 and Figure 3-11 illustrate how the multiplier hardware interprets data in Integer and Fractional modes.

The Integer or Fractional Multiplier Mode Select (IF) bit (CORCON[0]) determines the integer/fractional operation for the instructions listed in Table 3-4. The IF bit does not affect MCU multiply instructions listed in Table 3-5, which are always integer operations. The multiplier scales the result one bit to the left for fractional operation. The LSb of the result is always cleared. The multiplier defaults to Fractional mode for DSP operations at a device Reset.
Table 3-3. dsPIC33A Data Ranges
Register SizeInteger RangeFraction RangeFraction Resolution
16-Bit

-32768 to

32767

-1.0 to (1.0 – 2-15) (Q1.15 Format)

3.052x10-5
32-Bit

-2,147,483,648to

2,147,483,647

-1.0 to (1.0 – 2-31) (Q1.31 Format)

4.657x10-10
64-Bit

-9.223372037e18 to

9.223372037e18

-1.0 to (1.0 – 2-63) (Q.1.63 Format)

1.08420x10-19
72-Bit-2.361183241e21 to 2.361183241e21

-256.0 to (256.0 – 2-63) (Q.9.63 Format with 8 Guard bits)

1.08420x10-19
Figure 3-10. Integer and Fractional Representation of 0x40000001
Figure 3-11. Integer and Fractional Representation of 0xC0000002