3.3.18.3.1 Bit-Reversed Addressing Implementation

Bit-Reversed Addressing can only be enabled through the use of the movr.(w/l) instruction. This type of addressing is effective when used with pre-modified or post-modified destination addressing. The destination Bit-Reversed Addressing modifier is sourced from XBREV.XB[14:0].

If the length of a bit-reversed buffer is M = 2N bytes, the last ‘N’ bits of the data buffer start address must be zeros.

The XB[14:0] bits are the Bit-Reversed Addressing modifier, or ‘pivot point’, which is typically a constant. In the case of an FFT computation, its value is equal to half of the FFT data buffer size.

Note: All bit-reversed EA calculations assume either word size (where the least significant bit of every effective address is always clear) or long word size (where the two least significant bits of the effective address are always clear), based on the operation data width selected. The XB value is scaled accordingly to generate compatible (byte) addresses.

Bit-Reversed Addressing is only possible when using the MOVR instruction, and it can target a 16-bit or 32-bit-sized data. The MOVR instruction supports register indirect with Pre-Increment or Post-Increment Addressing and 16/32 bit-sized data writes. When Bit-Reversed Addressing is active, the W address pointer is always added to the address modifier (XB) and the offset associated with the Register Indirect Addressing mode is ignored. In addition, the LSb of each 16-bit address and the LS 2-bits of each 32-bit address will always be zero for both source and destination EAs. The MOVR instruction also supports “in-place” data reordering (where only one data buffer is used for both the source and destination). Source and destination indirect addressing may use the same register

Note: Modulo Addressing and Bit-Reversed Addressing can be enabled simultaneously using the same W register, but the Bit-Reversed Addressing operation will always take precedence for data writes when enabled.

If Bit-Reversed Addressing has already been enabled by setting the BREN (XBREV[15]) bit, a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the Bit-Reversed Pointer.

Figure 3-20. Bit-Reversed Addressing Example
Table 3-8. Bit-Reversed Addressing Sequence (16-Entry)
Normal AddressBit-Reversed Address
A3A2A1A0DecimalA3A2A1A0Decimal
0000000000
0001110008
0010201004
00113110012
0100400102
01015101010
0110601106
01117111014
1000800011
1001910019
10101001015
101111110113
11001200113
110113101111
11101401117
111115111115

32-Bit Data, Two Buffer Bit-Reversed Data Reordering Example

; Two buffer (input and output) bit reversed data re-order subroutine for 32-bit (real)
; data values
;
; W0: Temp
; W1: Data table size N (long words)
; W8: Input data table pointer (natural order) initialized to start of table
; W9: Output data table pointer (bit reversed) initialized to start of table

       push.l w0
       mov.sl #_XBREV, w0
       lsr.l w1, #1, [w0] ; XBREV = N/2

       sub.l #1, w1
       repeat w1
       movr.l [w8++], [w9++] ; Move data from input to output buffer, then
                             ; bump natural order and bit reversed pointers
       pop.l w0
       return