16.4.1 PWM Clock Control Register
| Name: | PCLKCON |
| Offset: | 0x1000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| HRRDY | HRERR | LOCK | |||||||
| Access | R | R/C | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIVSEL[1:0] | Reserved | MCLKSEL | |||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 1 | 0 | |||||
Bit 15 – HRRDY High-Resolution Ready bit
| Value | Description |
|---|---|
1 |
The High Resolution circuitry is ready. |
0 |
The High Resolution circuitry is not ready. |
Bit 14 – HRERR Hi-Resolution Error bit
| Value | Description |
|---|---|
1 |
An error has occurred during fine edge placement. If allowed to proceed, PWM signals will have limited resolution(FEP operates without the high resolution capability). |
0 |
No error has occurred. PWM signals will have full
resolution when HRRDY = 1. |
Bit 8 – LOCK Lock bit
| Value | Description |
|---|---|
1 |
Write-protected registers and bits are locked. |
0 |
Write-protected registers and bits are unlocked. |
Bits 5:4 – DIVSEL[1:0] PWM Clock Divider Selection bits
| Value | Description |
|---|---|
11 |
Divide ratio is 1:16. |
10 |
Divide ratio is 1:8. |
01 |
Divide ratio is 1:4 |
00 |
Divide ratio is 1:2 |
Bit 2 – Reserved
Reserved; maintain as '1'.
Bit 0 – MCLKSEL PWM Master Clock Selection bit
Note: Do not change the
MCLKSEL bit while ON (PGxCON[15]) =
1.