16.4.61 Auxiliary PWM Generator Current Limit PCI 2 Register(1)
Note:
- Caution should be exercised when modifying this register while PGxCON.ON = 1; unexpected results may occur.
- This bit has no effect when the
SWTERM control bit is used as the PCI Termination Event or if TERM[2:0] <
‘
101’.
| Name: | APGxCLPCI2 |
| Offset: | 0x1464, 0x14D8, 0x154C, 0x15C0 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PPS[31:24] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PPS[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PPS[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PPS[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:0 – PPS[31:0] PCI Polarity Select bits
| Value | Description |
|---|---|
1 |
Inverted |
0 |
Not inverted |