16.4.37 PWM Generator x Trigger F Register(1,2,3)
Note:
- This register cannot be modified while PGxSTAT.UPDATE = 1.
- The content of this register can be auto updated as part of the LLC mode of operation. Additionally, TRIGF is also dedicated the complementary output mode with max on-time adjustment. It is high resolution capable.
- The content of this register is reset at the end of every cycle.
- If HREN =
0, the four least significant bits are read as ‘0000’.
| Name: | PGxTRIGF |
| Offset: | 0x10B8, 0x112C, 0x11A0, 0x1214, 0x1288, 0x12FC, 0x1370, 0x13E4 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CAHALF | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TRIGF[19:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TRIGF[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TRIGF[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – CAHALF Specifies Where the Trigger Compare Time Occurs bit
| Value | Description |
|---|---|
1 |
The second phase of the center-aligned period |
0 |
The first phase of the center-aligned period |