55.19 FDPLL200M Electrical Specifications

Table 55-23. Frequency Digital Phase Locked Loop (FDPLL200M) Electrical Specifications
AC CHARACTERISTICS Standard Operating Conditions: VDD = AVDD = 1.71V to 3.63V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +85°C for Industrial Temperature
Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions
FDPLL200M (Fractional Digital Phase Locked Loop) (1)
FDPLL_1 FDPLL_FIN FDPLL Input Frequency Range 32 — 3200 kHz —
FDPLL_3 FDPLL_FOUT FDPLL Output Clock Frequency 96 — 200 MHz
FDPLL_5 FDPLL_Jitter (2) FDPLL Period Jitter Pk-to-Pk — — 2.7 % LDO Mode,

fEXTERNAL=32.768kHz PPM≤100,

fOUT(max)= 96MHz
— — 4.9 % LDO Mode,

fEXTERNAL=32.768kHz PPM≤100,

fOUT(max)= 200MHz
— — 3.0 % LDO Mode,

fEXTERNAL=3.2MHz PPM≤100,

fOUT(max)= 96MHz
— — 6.6 % LDO Mode,

fEXTERNAL=3.2MHz PPM≤100,

fOUT(max)= 200MHz
FDPLL_11 FDPLL_SRT (2) FDPLL Start-Up / Lock Time — — 95 µs fEXTERNAL=3.2MHz PPM≤100,
Note:
  1. FDPLL200M can be used only with LDO regulator.
  2. REFCLK for FDPLL200M is XOSC or XOSC32K.