55.16 XOSC32K Electrical Specifications

Table 55-20. XOSC32K Electrical Specifications
AC CHARACTERISTICS Standard Operating Conditions: VDD = AVDD = 1.71V to 3.63V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +85°C for Industrial Temperature
Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions
XOSC32_1 FOSC_XOSC32 XOSC32 Oscillator Crystal Frequency — 32.768 — kHz XIN32, XOUT32 Secondary Osc
XOSC32_3 CXIN32 XOSC32 XIN32 parasitic pin capacitance — 3.1 — pF —
XOSC32_5 CXOUT32 XOSC32 XOUT32 parasitic pin capacitance — 3.2 — pF —
XOSC32_11 CLOAD_X32 (3) 32.768 kHz Crystal Load Capacitance — — 12.5 pF XOSC32K.CGM = 1

XOSC32K.XTALEN = 1

XOSC32K.ENABLE = 1
XOSC32_12 — — 12.5 pF XOSC32K.CGM = 2

XOSC32K.XTALEN = 1

XOSC32K.ENABLE = 1
XOSC32_13 ESR_X32 32.768 kHz Crystal ESR — — 58 kΩ XOSC32K.CGM = 1

XOSC32K.XTALEN = 1

XOSC32K.ENABLE = 1

CLOAD = 12.5pF
XOSC32_14 — — 90 kΩ XOSC32K.CGM = 2

XOSC32K.XTALEN = 1

XOSC32K.ENABLE = 1

CLOAD = 12.5pF
XOSC32_15 TOSC32 TOSC32 = 1/FOSC_XOSC32 — 30.5176 — µs See parameter XOSC32_1 for

FOSC_XOSC32 value
XOSC32_17 XOSC32_ST (1) XOSC32 Crystal Start-up Time — 12000 Note (2) TOSC32 —
XOSC32_19 FOSC_XCLK32 Ext Clock Oscillator Input Freq (XIN32 pin) — 32.768 — kHz XOSC32K.XTALEN=0

XOSC32K.ENABLE = 1
XOSC32_21 XCLK32_DC Ext Clock Oscillator Duty Cycle 40 50 60 % XOSC32K.XTALEN=0

XOSC32K.ENABLE = 1
XOSC32_23 XCLK32_FST XIN32 Clock Fail Safe Time-out Period — 4*1/(LP32K_1/2^CFDCTRL.CFDPRESC) — ms LP32K_1: Refer to OSCULP32K Electrical Specifications
Note:
  1. This is for guidance only. A major component of crystal start-up time is based on the second party crystal MFG parasitics that are outside the scope of this specification. If this is a major concern the customer would need to characterize this based on their design choices.
  2. Maximum start up time user selectable in XOSC32K.STARTUP.
  3. CRYSTAL LOAD CAPACITOR CALCULATION GIVEN:
    • Standard PCB trace capacitance = 1.5 pF per 12.5 mm(0.5 inches) (i.e. PCB STD TRACE W=0.175 mm, H=36 μm, T=113 μm)
    • XTAL PCB capacitance typical therefore ~= 2.5pF for a tight PCB XTAL layout
    • For CXIN and CXOUT within 4pF of each other, Assume CXTAL_EFF = ((CXIN+CXOUT) / 2)
      Note: Averaging CXIN and CXOUT will effect final calculated CLOAD value by less than the tolerance of the capacitor selection.

      EQUATION 1:

      MFG CLOAD Spec = {( [CXIN + C1] * [CXOUT + C2] ) / [CXIN + C1 + C2 + CXOUT] } + estimated oscillator PCB stray capacitance

    • Assuming C1 = C2 and CXIN ~= CXOUT, the formula can be further simplified and restated to solve for C1 and C2 by:

      EQUATION 2: (i.e. Simplified Equation #1)

      C1 = C2 = ((2 * MFG CLOAD spec) - CXTAL_EFF - (2 * PCB capacitance))

      EXAMPLE ONLY:

    • XTAL Mfg CLOAD Data Sheet Spec = 12pF
    • PCB XTAL trace Capacitance = 2.5pF
    • CXIN pin = 6.5pF, CXOUT pin = 4.5pF therefore CXTAL_EFF = ((CXIN+CXOUT) / 2) CXTAL_EFF = ((6.5 + 4.5)/2) = 5.5pF

      C1 = C2 = ((2 * MFG CLOAD spec) - CXTAL_EFF - (2 * PCB capacitance))

      C1 = C2 = (24 - 5.5 - (2 * 2.5))

      C1 = C2 = (24 - 5.5 - 5)

      C1 = C2 = 13.5pF (Always rounded down)

      C1 = C2 = 13pF (i.e. for hypothectical example crystal external load capacitors)

      User C1=C2=13pF ≤ CLOAD_X32(max) specification