55.18 DFLL48M Electrical Specifications

Table 55-22. Digital Frequency Locked Loop (DFLL48M) Electrical Specifications
AC CHARACTERISTICS Standard Operating Conditions: VDD = AVDD = 1.71V to 3.63V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +85°C for Industrial Temperature
Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions
DFLL48M (Open Loop) (1,2)
DFLL_1 DFLL_OL_FOUT DFLL Open Loop Clock Frequency 45.8 48 49.3 MHz LDO Mode
DFLL_9 DFLL_OL_SRT Start-Up (Ready bit valid) — — 7 µs LDO Mode

FOUT within 90% of final value
DFLL48M (Closed Loop) (1,3,4,6)
DFLL_11 DFLL_CL_FIN DFLL Closed loop Input Frequency Range 732 32768 33000 Hz LDO Mode
DFLL_13 DFLL_CL_FOUT DFLL Closed Loop Clock Frequency — 47.972 — MHz LDO Mode

XOSC32 32.768kHz PPM≤100,

DFLLMUL = 1464
DFLL_15 DFLL_CL_Jitter DFLL Period Jitter Pk-to-Pk — — 2 % LDO Mode

XOSC32 32.768kHz PPM≤100,

DFLLMUL = 1464
DFLL_21 DFLL_CL_SRT (5) DFLL Closed Loop Mode / Lock Time — — 1145 µs LDO Mode

XOSC32 32.768kHz PPM≤100,

DFLLMUL = 1464
Note:
  1. DFLL48 in open or close loop can be used only with LDO regulator.
  2. Not recommended for functional USB operation, SOF sync start-up only.
  3. In Closed loop mode the DFLL can use a variety of clock sources. The DFLL can be trimmed using register DFLLMUL.
  4. To ensure that the device stays within the maximum allowed clock frequency, any reference clock for DFLL in close loop must be within a 2% error accuracy.
  5. DFLLMUL = 1464, DFLLCTRL.BPLCKC = 1: only fine value change, coarse value locked to the reset value.

    DFLLCTRL.QLDIS = 0: quick lock enable,

    DFLLCTRL.CCDIS = 1: Enabling chill cycles might double the lock time.

    DFLLMUL.FSTEP = 10 : Max fine step size, divided or dividing into two parts, search. 10 is a optimum value.

  6. During a maximum 30 cycles of the reference clock period, between lock flag asserted and frequency stabilization, DFLL accuracy will be limited.

    To minimize the cycle-to-cycle jitter during lock search, in addition to selecting a low step value (DFLLMUL.FSTEP, DFLLMUL.CSTEP), it is recommended to disable the Quick Lock feature.