55.32 USB Electrical Specifications

Table 55-45. USB Electrical Specifications
AC CHARACTERISTICS Standard Operating Conditions: VDD = AVDD = 1.71V to 3.63V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +85°C for Industrial Temperature
Param. No. Symbol Characteristics(1) Min. Typ. Max. Units Conditions
USB_1 VDDUSB USB Transceiver Voltage 3 — 3.6 V Voltage on VDD must be in this range for proper USB operation
VBUS Supply
USB_7 VILUSB Input Low Voltage for USB Buffer — — 0.8 V —
USB_9 VIHUSB Input High Voltage for USB Buffer 2 — — V —
USB_11 VDIFS Differential Input Sensitivity 0.2 — — V The difference between D+ and D- must exceed this value while VCM is met
USB_13 VCM Differential Common Mode Range 0.8 — 2.5 V VDDUSB = 3.0V-to-3.6V
USB_15 ZOUT Driver Output Impedance 28 — 44 Ω —
USB_17 VOLUSB Voltage Output Low — — 0.3 V 1.425 kΩ load connected to VUSB=3.6V
USB_19 VOHUSB Voltage Output High 2.8 — — V 14.25 kΩ load connected to ground w/VUSB=3.0V
USB_23 USBCLKS USB Clock Source (1) GCLK_USB of 48 MHz ± 0.25% — 48 — MHz GCLK_USB = 48 MHz ± 0.25%
USB_25 USBAHB Min. AHB Clock for USB Operations 12 — — MHz —
Note:
  1. External Crystal or clock oscillator ppm ≤ 50 w/FDPLL only for GCLK_USB_ of 48 MHz ± 0.25%.
Table 55-46. USB Clock Configuration
USB Clock configuration Standard Operating Conditions: VDD = AVDD = 1.71V to 3.63V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +85°C for Industrial Temperature
Param. No. Symbol Characteristics Device mode operation. Host mode operation.
USB_30 USB_GCLK_SRC DFLL48M Open loop No No
DFLL48M Close loop, Ref. internal OSC source No No
DFLL48M Close loop, Ref. external XOSC source Yes No
DFLL48M Close loop, Ref. SOF (USB recovery mode) Yes (1) N/A
FDPLL internal OSC (32K, 8M…) No No
FDPLL external OSC (<1MHz) Yes No
FDPLL external OSC (>1MHz) Yes (2) Yes
Note:
  1. When using DFLL48M in USB recovery mode, the Fine Step value must be 0x0A to guarantee a USB clock at +/-0.25% before 11ms after a resume. Only usable in LDO regulator mode.
  2. FDPLL lock time is short when the clock frequency source is high (>1 MHz). Therefore, FDPLL and external OSC can be stopped during USB suspend mode to reduce consumption and guarantee a USB resume signal time (See USB specification).