18.4.13 Timer 64 Control Register
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| 31:3 | Reserved | R/W | 0 | Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. |
| 2 | TIM64INTEN | R/W | 0 | Timer 64 interrupt enable. When the counter reaches zero, an interrupt is signaled to the Cortex-M3 processor NVIC. 0: Timer 64 interrupt disabled 1: Timer 64 interrupt enabled |
| 1 | TIM64MODE | R/W | 0 | Timer 64 mode. 0: Timer 64 in Periodic mode If TIM64ENABLE = 1 when the counter reaches zero, the counter is reloaded from the value in the TIM64_LOADVAL_U and TIM64_LOADVAL_L registers and starts the counting down. 1: Timer 64 in One-shot mode If TIM64ENABLE = 1 when the counter reaches zero, the counter stops counting. To restart the counter, load TIM64_LOADVAL_U and TIM64_LOADVAL_L with a non-zero value or set the Timer to Periodic mode by clearing TIM64MODE to 0. |
| 0 | TIM64ENABLE | R/W | 0 | Timer 64 enable. 0: Timer 64 disabled 1: Timer 64 enabled Writing this register when the Timer is set to 32-bit mode has no effect. Reading this register when the Timer is set to 32-bit mode returns the reset value. |