18.4.6 Timer x Masked Interrupt Status Register
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| 31:1 | Reserved | R | 0 | Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. |
| 0 | TIMx_MIS | R | 0 | Timer x masked interrupt status (MIS) This read only bit is a logical AND of the TIMxRIS and TIMxINTEN bits. The TIMERxINT output from the Timer has the same value as this bit. Writing to this bit has no effect. Reading this register when the Timer is set to 64-bit mode returns the reset value. |