18.4.15 Timer 64 Masked Interrupt Status Register
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| 31:1 | Reserved | R | 0 | Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. |
| 0 | TIM64_MIS | R | 0 | Timer 64 masked interrupt status. This read only bit is a logical AND of the TIM64RIS and TIM64INTEN bits. The TIMER64INT output from the Timer has the same value as this bit. Writing to this bit has no effect. |