7.4.1.17 Descriptor 3 Status Register

Table 7-19. HPDMAD3SR_REG
Bit NumberNameReset ValueDescription
0HPDMASR_DCP_ACTIVE[3]0Descriptor 3 transfer is in progress.

1: Descriptor 3 transfer is in progress.

0: Descriptor 3 is in queue when HPDMACR_DCP_VALID[3] bit is set in descriptor 3 Control register.

1HPDMASR_DCP_CMPLET[3]0Descriptor 2 transfer complete.

1: Descriptor 3 transfer completed successfully.

0: Descriptor 3 transfer not completed.

This bit clears on writing ‘1’ to HPDMAICR_CLR_XFR_INT[3] of the descriptor 3 Control register.

2HPDMASR_DCP_SERR[3]0Descriptor 3 source transfer error.

1: Descriptor 3 transfer error occurred at source end.

0: No error at source end during descriptor 3 transfer

This bit clears on writing ‘1’ to HPDMAICR_CLR_XFR_INT[3] of the descriptor 3 Interrupt Clear register.

3HPDMASR_DCP_DERR[3]0Descriptor 3 destination transfer error.

1: Descriptor 3 transfer error

0: No error at destination end during descriptor 3 transfer

This bit clears on writing ‘1’ to HPDMAICR_CLR_XFR_INT[3]

of the descriptor 3 Interrupt Clear register

31:4Reserved0Software must not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit must be preserved across a read-modify-write operation.