7.4.1.15 Descriptor 1 Status Register

Table 7-17. HPDMAD1SR_REG
Bit NumberNameReset ValueDescription
0HPDMASR_DCP_ACTIVE[1]0Descriptor 1 transfer is in progress.

1: Descriptor 1 transfer is in progress.

0: Descriptor 1 is in queue when HPDMACR_DCP_VALID[1] bit is set in Descriptor 1 Control register.

1HPDMASR_DCP_CMPLET[1]0Descriptor 1 transfer complete.

1: Descriptor 1 transfer completed successfully

0: Descriptor 1 transfer not completed

This bit clears on writing ‘1’ to HPDMAICR_CLR_XFR_INT[1]

of the descriptor 1 Control register.

2HPDMASR_DCP_SERR[1]0Descriptor 1 source transfer error.

1: Descriptor 1 transfer error occurred at source end

0: No error at source end during descriptor 1 transfer

This bit clears on writing ‘1’ to HPDMAICR_CLR_XFR_INT[1] of the descriptor 1 Interrupt Clear register.

3HPDMASR_DCP_DERR[1]0Descriptor 1 destination transfer error.

1: Descriptor 1 transfer error

0: No error at destination end during descriptor 1 transfer

This bit clears on writing ‘1’ to HPDMAICR_CLR_XFR_INT[1] of the descriptor 1 Interrupt Clear register.

31:4Reserved0Software must not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit must be preserved across a read-modify-write operation.