7.4.1.16 Descriptor 2 Status Register 

Table 7-18. HPDMAD2SR_REG
Bit NumberNameReset ValueDescription
0HPDMASR_DCP_ACTIVE[2]0Descriptor 2 transfer is in progress.

1: Descriptor 2 transfer is in progress.

0: Descriptor 2 is in queue when HPDMACR_DCP_VALID[2] bit is set in descriptor 2 Control register.

1HPDMASR_DCP_CMPLET[2]0Descriptor 2 transfer complete.

1: Descriptor 2 transfer completed successfully.

0: Descriptor 2 transfer not completed.

This bit clears on writing ‘1’ to HPDMAICR_CLR_XFR_INT[2] of the descriptor 2 Control register.

2HPDMASR_DCP_SERR[2]0Descriptor 2 source transfer error.

1: Descriptor 2 transfer error occurred at source end

0: No error at source end during descriptor 2 transfer

This bit clears on writing ‘1’ to HPDMAICR_CLR_XFR_INT[2] of the descriptor 2 Interrupt Clear register.

3HPDMASR_DCP_DERR[2]0Descriptor 2 destination transfer error.

1: Descriptor 2 transfer error

0: No error at destination end during descriptor 2 transfer

This bit clears on writing ‘1’ to HPDMAICR_CLR_XFR_INT[2] of the descriptor 2 Interrupt Clear register.

31:4Reserved0Software must not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit must be preserved across a read-modify-write operation.