7.4.1.10 Descriptor 0 Control Register

Table 7-12. HPDMAD0CR_REG
Bit Number	Name	Description
15:0	HPDMACR_DCP0_XFR_SIZE	Descriptor 0 transfer size in bytes. Defines number of bytes to be transferred in a descriptor 0 transfer. All zeros in this field indicates 64 KB transfers. As all the transfers are word aligned, 2 LSBs 1:0 are ignored.
16	HPDMACR_DCP_VALID[0]	1: Indicates the descriptor 0 is valid and ready to transfer. On completing descriptor 0 transfer, the HPDMA controller clears this bit. Once the descriptor valid bit is set, descriptor fields such as Source address, Destination Address, Transfer size, and Descriptor Valid bits cannot be overwritten. When this bit is set, HPDMA clears the status of the previous transfer, which includes transfer complete, transfer error interrupts, and corresponding descriptor 0 Status Register.
17	HPDMACR_XFR_DIR[0]	Descriptor 0 data transfer direction. 0: AHB bus matrix to MSS DDR bridge 1: MSS DDR bridge to AHB bus matrix
18	HPDMACR_DCP_CLR[0]	When this bit is set, HPDMA clears the descriptor 0 fields. HPDMA terminates the current transfer and reset descriptor status and control registers. This bit is always read back as zero.
19	HPDMACR_DCP_PAUSE[0]	1: HPDMA pauses descriptor 0 transfers, does idle transfers. 0: HPDMA resumes descriptor 0 transfers from where they have stopped.
20	HPDMACR_XFR_CMP_INT[0]	1: HPDMA asserts interrupt on completion of descriptor 0 transfers without error. 0: HPDMA will not generate transfer complete interrupt.
21	HPDMACR_XFR_ERR_INT[0]	1: HPDMA asserts transfer error interrupt on error during descriptor 0 transfers. 0: HPDMA will not generate transfer error interrupt.
22	HPDMACR_NON_WORD_INT[0]	Non-word interrupt enable. 1: HPDMA asserts transfer error interrupt when non-word aligned transfer size is programmed in HPDMACR_DCP0_XFR_SIZE and HPDMA continues the same descriptor transfer. 0: HPDMA will not generate interrupt.
31:23	Reserved	Software must not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit must be preserved across a read-modify-write operation.