7.4.1.1 HPDMA Empty Descriptor Register

1: Descriptor 0 is empty and ready to configure.
0: Descriptor 0 is already configured and descriptor transfer is in progress/queue.

At the end of the descriptor transfer, either on transfer error or transfer done, the HPDMA controller asserts this bit High.

1: Descriptor 1 is empty and ready to configure.
0: Descriptor 1 is already configured and descriptor transfer is in progress/queue.

At the end of the descriptor transfer, either on transfer error or transfer done, the HPDMA controller asserts this bit High.

1: Descriptor 2 is empty and ready to configure.
0: Descriptor 2 is already configured and descriptor transfer is in progress/queue.

At the end of the descriptor transfer, either on transfer error or transfer done, the HPDMA controller asserts this bit High.

1: Descriptor 3 is empty and ready to configure.
0: Descriptor 3 is already configured and descriptor transfer is in progress/queue.

At the end of the descriptor transfer, either on transfer error or transfer done, the HPDMA controller asserts this bit High.

1: Descriptor 0 transfer completed successfully.
0: Descriptor 0 transfer not completed.

When the descriptor 0 transfer is completed, either with transfer error or transfer done, HPDMA controller asserts this bit High.

This bit is cleared on writing ‘1’ to the HPDMAICR_CLR_XFR_INT[0] bit of the HPDMA Interrupt Clear register or when the HPDMACR_DCP_VALID[0] bit of descriptor 0 Control register is set.

1: Descriptor 1 transfer completed successfully.
0: Descriptor 1 transfer not completed.

When the descriptor 1 transfer is completed, either with transfer error or transfer done, the HPDMA controller asserts this bit High.

This bit is cleared on writing ‘1’ to the HPDMAICR_CLR_XFR_INT[1] bit of the HPDMA Interrupt Clear register or when the HPDMACR_DCP_VALID[1] bit of the descriptor 1 Control register is set.

1: Descriptor 2 transfer completed successfully
0: Descriptor 2 transfer not completed

When the descriptor 2 transfer is completed, either with transfer error or transfer done, the HPDMA controller asserts this bit High.

This bit is cleared on writing ‘1’ to the HPDMAICR_CLR_XFR_INT[2] bit of the HPDMA Interrupt Clear register or when the HPDMACR_DCP_VALID[2] bit of the descriptor 2 Control register is set.

1: Descriptor 3 transfer completed successfully
0: Descriptor 3 transfer not completed

When the descriptor 3 transfer is completed, either with transfer error or transfer done, the HPDMA controller asserts this bit High.

This bit is cleared on writing ‘1’ to the HPDMAICR_CLR_XFR_INT[3] bit of the HPDMA Interrupt Clear Register or when the HPDMACR_DCP_VALID[3] bit of the descriptor 3 control register is set.

1: Descriptor 0 transfer error 
0: No descriptor 0 transfer error

This bit is asserted High if an error occurs during the descriptor 0 transfer at either source or destination end. This bit is cleared on writing ‘1’ to the HPDMAICR_CLR_XFR_INT[0] bit of the HPDMA Interrupt Clear register or when the HPDMACR_DCP_VALID[0] bit of the descriptor 0 control register is set.

1: Descriptor 1 transfer error 
0: No descriptor 1 transfer error

This bit is asserted High, if an error occurs during the descriptor 1 transfer at either source or destination end. This bit is cleared on writing ‘1’ to HPDMAICR_CLR_XFR_INT[1] of the HPDMA Interrupt Clear register, or when the HPDMACR_DCP_VALID[1] bit of Descriptor 1 control register is set.

1: Descriptor 2 transfer error 
0: No descriptor 2 transfer error

This bit is asserted High, if an error occurs during the descriptor 2 transfer at either source or destination end. This bit is cleared on writing ‘1’ to the HPDMAICR_CLR_XFR_INT[2] bit of the HPDMA Interrupt Clear register, or when the HPDMACR_DCP_VALID[2] bit of the descriptor 2 control register is set.

1: Descriptor 3 transfer error 
0: No descriptor 3 transfer error

This bit is asserted High, if an error occurs during the descriptor 3 transfer at either source or destination end. This bit is cleared on writing ‘1’ to HPDMAICR_CLR_XFR_INT[3] of the HPDMA Interrupt Clear register, or when the HPDMACR_DCP_VALID[3] bit of the descriptor 3 control register is set.

1: Descriptor 0 non-word aligned transfer size error
0: No non-word aligned transfer size error

This bit is asserted High, if non-word aligned value is configured in descriptor 0 transfer size field. This bit is cleared on writing ‘1’ to HPDMAICR_NON_WORD_INT[0] of the HPDMA Interrupt Clear register, or when the HPDMACR_DCP_VALID[0] bit of the descriptor 0 Control register is set or when the HPDMACR_DCP_CLR[0] bit of the HPDMA Controller register is set.

In this case, HPDMA will continue the transfer by ignoring the 2 LSBs of the transfer size field.

1: Descriptor 1 non-word aligned transfer size error
0: No non-word aligned transfer size error

This bit is asserted High if a non-word aligned value is configured in the descriptor 1 transfer size field.

This bit is cleared on writing ‘1’ to HPDMAICR_NON_WORD_INT[1] of the HPDMA Interrupt Clear register, or when the HPDMACR_DCP_VALID[1] bit of the descriptor 1 Control register is set, or when the HPDMACR_DCP_CLR[1] bit of the HPDMA Controller register is set.

In this case, HPDMA will continue the transfer by ignoring the 2 LSBs of the transfer size filed.

1: Descriptor 2 non-word aligned transfer size error
0: No non-word aligned transfer size error

This bit is asserted High if a non-word aligned value is configured in the descriptor 2 transfer size field.

This bit is cleared on writing ‘1’ to HPDMAICR_NON_WORD_INT[2] of the HPDMA Interrupt Clear register, or when the HPDMACR_DCP_VALID[2] bit of the descriptor 2 Control register is set, or when the HPDMACR_DCP_CLR[2] bit of the HPDMA Controller register is set.

In this case, HPDMA will continue the transfer by ignoring the 2 LSBs of the transfer size field.

1: Descriptor 3 non-word aligned transfer size error
0: No non-word aligned transfer size error

This bit is asserted High, if a non-word aligned value is configured in the descriptor 3 transfer size field.

This bit clears on writing ‘1’ to HPDMAICR_NON_WORD_INT[3] of the HPDMA Interrupt Clear register, or when the HPDMACR_DCP_VALID[3] bit of the descriptor 3 Control register is set, or when the HPDMACR_DCP_CLR[3] bit of the HPDMA Controller register is set.

In this case, HPDMA will continue the transfer by ignoring the 2 LSBs of transfer size field.