7.4.1.21 Descriptor 3 Pending Transfers Register
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| 15:0 | HPDMAPTR_D3_SRC_PNDNG | 0 | Descriptor 3 source pending transfers in words. This register indicates the internal transfer size counter corresponding to the source end of descriptor 3. At the end of the transfer, zero in this register indicates the successful transfer, and a non-zero value indicates error occurrence at the source during descriptor 0 transfer. |
| 31:16 | HPDMAPTR_D3_DST_PNDNG | 0 | Descriptor 3 destination pending transfers in words. This register indicates the internal transfer size counter corresponding to the destination end of descriptor 3. At the end of the transfer, zero in this register indicates the successful transfer, and a non-zero value indicates error occurrence at the destination during descriptor 3 transfer. |