7.4.1.14 Descriptor 0 Status Register

Table 7-16. HPDMAD0SR_REG
Bit NumberNameReset ValueDescription
0HPDMASR_DCP_ACTIVE[0]0Descriptor 0 transfer in progress.

1: Descriptor 0 transfer in progress.

0: Descriptor 0 is in queue when HPDMACR_DCP_VALID[0] bit is set in descriptor 0 Control register.

1HPDMASR_DCP_CMPLET[0]0Descriptor 0 transfer complete.

1: Descriptor 0 transfer completed successfully

0: Descriptor 0 transfer not completed

This bit clears on writing ‘1’ to HPDMAICR_CLR_XFR_INT[0] of the descriptor 0 control register.

2HPDMASR_DCP_SERR[0]0Descriptor 0 source transfer error.

1: Descriptor 0 transfer error occurred at source end.

0: No error at source end during descriptor 0 transfer

This bit clears on writing ‘1’ to HPDMAICR_CLR_XFR_INT[0] of the descriptor 0 Interrupt Clear register.

3HPDMASR_DCP_DERR[0]0Descriptor 0 destination transfer error.

1: Descriptor 0 transfer error

0: No error at destination end during descriptor 0 transfer.

This bit clears on writing ‘1’ to HPDMAICR_CLR_XFR_INT[0] of the descriptor 0 Interrupt Clear register.

31:4Reserved0Software must not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit must be preserved across a read-modify-write operation.