20.2.6.1.4 M3_SYS_RESET_N

M3_SYS_RESET_N resets the Cortex-M3 processor core and its components, excluding the debug logic.

This reset is generated based on M3_RESET_ M3_CLK_N and SYSRESET_N. M3_RESET_M3_CLK_N is a synchronized signal of M3_RESET_N from the FPGA fabric on M3_CLK. The following figure shows the generation of M3_SYS_RESET_N.

In the five Cortex-M3 processor resets, M3_SYS_RESET_N is the only reset signal that can be controlled.

M3_RESET_N is an active-low reset input from the FPGA fabric and resets the Cortex-M3 processors if set to 0. It is only usable in order to extend the duration of the system reset to the Cortex-M3 processor after the rest of the MSS has been released from reset. This allows to perform a secure hardware based code shadowing function, thereby minimizing boot time.