4.2.5.6 eNVM Program and Verify Operations Timing Diagrams

Timing diagrams in this section illustrate eNVM Program and Verify operations at the AHB bus transfer level with the Cortex-M3 processor operating at 166 MHz. The eNVM NV_FREQRNG is set to 15. The sample eNVM operation programs the eNVM sector 0 page 4 with random data and verifies the eNVM sector 0 page 4.

Note: In all the waveforms, the eNVM controller register offset is shown in AHB address line (HADDR). Refer to 4.6 eNVM Control Registers for more information.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.