2.7.2.14 HardFault Status Register

The HFSR gives information about events that activate the HardFault handler. See the register summary in Table 2-44 for its attributes.

This register is read, write to clear. This means that bits in the register read normally, but writing 1 to any bit clears that bit to 0. The bit assignments are:

Figure 2-40. HFSR Bit Assignments
Table 2-61. HFSR Bit Assignments
Bits Name Function
[31] DEBUGEVT Reserved for Debug use. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable.
[30] FORCED Indicates a forced HardFault, generated by escalation of a fault with configurable priority that cannot be handles, either because of priority or because it is disabled:

0: no forced HardFault

1: forced HardFault.

When this bit is set to 1, the HardFault handler must read the other fault status registers to find the cause of the fault.
[29:2] Reserved.
[1] VECTTBL Indicates a BusFault on a vector table read during exception processing:

0: no BusFault on vector table read

1: BusFault on vector table read.

This error is always handled by the HardFault handler.

When this bit is set to 1, the PC value stacked for the exception return points to the instruction that was preempted by the exception.
[0] Reserved.

The HFSR bits are sticky. This means as one or more fault occurs, the associated bits are set to 1. A bit that is set to 1 is cleared to 0 only by writing 1 to that bit, or by a reset.