2.7.2.7 Configuration and Control Register

The CCR controls entry to Thread mode and enables:

the handlers for NMI, HardFault and faults escalated by FAULTMASK to ignore BusFaults
trapping of divide by zero and unaligned accesses
access to the STIR by unprivileged software, see 2.7.1.9 Software Trigger Interrupt Register.

See the register summary in Table 2-44 for the CCR attributes.

The bit assignments are:

Figure 2-32. CCR Bit Assignments

Table 2-52. CCR Bit Assignments
Bits	Name	Function
[31:10]		Reserved.
[9]	STKALIGN	Indicates stack alignment on exception entry: 0: 4-byte aligned 1: 8-byte aligned. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment.
[8]	BFHFNMIGN	Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. This applies to the HardFault, NMI, and FAULTMASK escalated handlers: 0: data BusFaults caused by load and store instructions cause a lock-up 1: data BusFaults caused by load and store instructions are ignored. Set this bit to 1 only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect problems.
[7:5]		Reserved.
[4]	DIV_0_TRP	Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0: 0: do not trap divide by 0 1: trap divide by 0. When this bit is set to 0, a divide by zero returns a quotient of 0.
[3]	UNALIGN_TRP	Enables unaligned access traps: 0: do not trap unaligned halfword and word accesses 1: trap unaligned halfword and word accesses. If this bit is set to 1, an unaligned access generates a UsageFault. Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of whether UNALIGN_TRP is set to 1.
[2]		Reserved.
[1]	USERSETMPEND	Enables unprivileged software access to the STIR, see 2.7.1.9 Software Trigger Interrupt Register: 0: disable 1: enable
[0]	NONBASETHRDENA	Indicates how the processor enters Thread mode: 0: processor can enter Thread mode only when no exception is active. 1: processor can enter Thread mode from any level using the appropriate EXC_RETURN value, see 2.5.3.7.2 Exception Return.

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