2.7.2.3 Interrupt Control and State Register

The ICSR:

  • Provides:
    • A set-pending bit for the Non-Maskable Interrupt (NMI) exception
    • Set-pending and clear-pending bits for the PendSV and SysTick exceptions
  • Indicates:
    • The exception number of the exception being processed
    • Whether there are preempted active exceptions
    • The exception number of the highest priority pending exception
    • Whether any interrupts are pending

See the register summary in Table 2-44, and the Type descriptions in the following table, for the ICSR attributes. The bit assignments are:

Figure 2-28. ICSR Bit Assignments
Table 2-47. ICSR Bit Assignments
Bits Name Type Function
[31] NMIPENDSET RW NMI set-pending bit.

Write:

  • 0: no effect
  • 1: changes NMI exception state to pending.

Read:

  • 0: NMI exception is not pending
  • 1: NMI exception is pending.

Because NMI is the highest-priority exception, normally the processor enter the NMI exception handler as soon as it registers a write of 1 to this bit, and entering the handler clears this bit to 0. A read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
[30:29] Reserved.
[28] PENDSVSET RW PendSV set-pending bit.

Write:

  • 0: no effect
  • 1: changes PendSV exception state to pending

Read:

  • 0: PendSV exception is not pending
  • 1: PendSV exception is pending

Writing 1 to this bit is the only way to set the PendSV exception state to pending.
[27] PENDSVCLR WO PendSV clear-pending bit.

Write:

  • 0: no effect
  • 1: removes the pending state from the PendSV exception
[26] PENDSTSET RW SysTick exception set-pending bit.

Write:

  • 0: no effect
  • 1: changes SysTick exception state to pending

Read:

  • 0: SysTick exception is not pending
  • 1: SysTick exception is pending
[25] PENDSTCLR WO SysTick exception clear-pending bit.

Write:

  • 0: no effect
  • 1: removes the pending state from the SysTick exception

This bit is WO. On a register read its value is Unknown.
[24] Reserved.
[23] Reserved for Debug use RO This bit is reserved for Debug use and reads-as-zero when the processor is not in Debug.
[22] ISRPENDING RO Interrupt pending flag, excluding NMI and Faults:
  • 0: interrupt not pending
  • 1: interrupt pending
[21:18] Reserved.
[17:12] VECTPENDING RO Indicates the exception number of the highest priority pending enabled exception:
  • 0: no pending exceptions
  • Nonzero: the exception number of the highest priority pending enabled exception

The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register.
[11] RETTOBASE RO Indicates whether there are preempted active exceptions:
  • 0: there are preempted active exceptions to execute
  • 1: there are no active exceptions, or the currently-executing exception is the only active exception
[10:9] Reserved.
[8:0] VECTACTIVEa RO Contains the active exception number:
  • 0: Thread mode
  • Nonzero: The exception number1 of the currently active exception.

Subtract 16 from this value to obtain the CMSIS IRQ number required to index into the Interrupt Clear-Enable, Set-Enable, Clear-Pending, Set-Pending, or Priority Registers, see Table 2-5.
Note:
  1. This is the same value as IPSR bits[8:0], see 2.5.1.3.7 Interrupt Program Status Register.

When you write to the ICSR, the effect is unpredictable if you:

  • Write 1 to the PENDSVSET bit and write 1 to the PENDSVCLR bit
  • Write 1 to the PENDSTSET bit and write 1 to the PENDSTCLR bit