2.7.2.1 Auxiliary Control Register

The ACTLR provides disable bits for the following processor functions:

  • IT folding
  • write buffer use for accesses to the default memory map
  • interruption of multi-cycle instructions.

By default this register is set to provide optimum performance from the Cortex-M3 processor, and does not normally require modification.

See the register summary in the preceding table for the ACTLR attributes. The bit assignments are:

Figure 2-26. ACTLR Bit Assignments
Table 2-45. ACTLR Bit Assignments
Bits Name Function
[31:3] Reserved
[2] DISFOLD When set to 1, disables the ability of the Cortex-M3 processor to execute an IT instruction in parallel with a neighboring instruction.
[1] DISDEFWBUF When set to 1, disables write buffer use during default memory map accesses. This causes all BusFaults to be precise BusFaults but decreases performance because any store to memory must complete before the processor can execute the next instruction. This bit only affects write buffers implemented in the Cortex-M3 processor.
[0] DISMCYCINT When set to 1, disables interruption of load multiple and store multiple instructions. This increases the interrupt latency of the processor because any LDM or STM must complete before the processor can stack the current state and enter the interrupt handler.