Note: SFR bit availability is defined in Table 14-1 through Table 14-4 for each device variant and port, respectively.
Table 14-14. Register Bit Attribute Legend
Symbol
Description
Symbol
Description
Symbol
Description
R
Readable
bit
HC
Cleared by
Hardware
(Gray
cell)
Unimplemented
W
Writable
bit
HS
Set by
Hardware
X
Bit is unknown
at Reset
C
Write to
clear
S
Software
settable bit
x
Channel
number
Name:
PORTx
Offset:
0x0200, 0x0214, 0x0228,
0x023C
Bit
31
30
29
28
27
26
25
24
ALTPORTx[15:8]
Access
R/W/HS/HC
R/W/HS/HC
R/W/HS/HC
R/W/HS/HC
R/W/HS/HC
R/W/HS/HC
R/W/HS/HC
R/W/HS/HC
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
ALTPORTx[7:0]
Access
R/W/HS/HC
R/W/HS/HC
R/W/HS/HC
R/W/HS/HC
R/W/HS/HC
R/W/HS/HC
R/W/HS/HC
R/W/HS/HC
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
PORTx[15:8]
Access
R/W/HS/HC
R/W/HS/HC
R/W/HS/HC
R/W/HS/HC
R/W/HS/HC
R/W/HS/HC
R/W/HS/HC
R/W/HS/HC
Reset
x
x
x
x
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PORTx[7:0]
Access
R/W/HS/HC
R/W/HS/HC
R/W/HS/HC
R/W/HS/HC
R/W/HS/HC
R/W/HS/HC
R/W/HS/HC
R/W/HS/HC
Reset
0
0
0
0
0
0
0
0
Bits 31:16 – ALTPORTx[15:0] Alternate PORTx Data
Input Value bits
Bits 15:0 – PORTx[15:0] PORTx Data Input Value bits
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