14.3.21 Peripheral Pin Select Input Register 9

Table 14-34. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	RPINR9
Offset:	0x3928


Bit	31	30	29	28	27	26	25	24
	U2CTSR[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	U2RXR[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	U1CTSR[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	U1RXR[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:24 – U2CTSR[7:0] Assign UART2 Clear-to-Send (U2CTS) to the Corresponding RPn Pin bits

Bits 23:16 – U2RXR[7:0] Assign UART2 Receive (U2RX) to the Corresponding RPn Pin bit

Bits 15:8 – U1CTSR[7:0] Assign UART1 Clear-to-Send (U1CTS) to the Corresponding RPn Pin bits

Bits 7:0 – U1RXR[7:0] Assign UART1 Receive (U1RX) to the Corresponding RPn Pin bit

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