14.3.52 IOIM x Control Register

Table 14-44. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	IOIMxCON
Offset:	0x1E90, 0x1E9C, 0x1EA8, 0x1EB4


Bit	31	30	29	28	27	26	25	24
					FLTINJ	OKINJ	ATEST[1:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	23	22	21	20	19	18	17	16
	EOVFV[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	ON		SLPEN	SIDL		EXTCLK
Access	R/W		R/W	R/W		R/W
Reset	0		0	0		0


Bit	7	6	5	4	3	2	1	0
	FBKSEL[3:0]				REFSEL[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 27 – FLTINJ Fault Injection bit

A write of ‘1’ to this bit will simulate a comparison mismatch event. The ERR bit will become set, the ERRCNT will increment to EOVFV and the OVF will be set if the ERRCNT overflows.

Bit 26 – OKINJ OK Inject bit

A write of ‘1’ to this bit will simulate a transition on the reference signal input, blanking time insertion and a good comparison between reference and feedback signals. The OK bit will be set.

Bits 25:24 – ATEST[1:0] Artificial Test Enable bit

Value	Description
11	Artificial OKINJ Test is enabled
10	Artificial FLTINJ Test is enabled
01	Artificial Test disabled
00	Artificial Test disabled

Bits 23:16 – EOVFV[7:0] Error-counter Overflow Value bits

Bit 15 – ON Module Enable bit

Value	Description
1	IOIM module is enabled
0	IOIM module is disabled

Bit 13 – SLPEN Module Sleep Enable bit

Value	Description
1	Module operates in Sleep mode
0	Module disabled in Sleep mode

Bit 12 – SIDL Module Stop in Idle Mode Enable bit

Value	Description
1	Module disabled in Idle mode
0	Module operates in Idle mode

Bit 10 – EXTCLK External Clock Source Enable bit

Value	Description
1	CLKGEN13 (200 MHz)
0	T_CY (Instruction Cycle) (default)

Bits 7:4 – FBKSEL[3:0] Feedback Input Mux Selection bits

Value	Description
1111	Feedback input [15] is selected
...
0001	Feedback input [1] is selected
0000	Feedback input [0] is selected

Bits 3:0 – REFSEL[3:0] Reference Input Mux Selection bits

Value	Description
1111	Reference input [15] is selected
...
0001	Reference input [1] is selected
0000	Reference input [0] is selected