14.3.3 Output Enable for TRISx Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | TRISx |
| Offset: | 0x0208, 0x021C, 0x0230, 0x0244 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ALTTRISx[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ALTTRISx[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TRISx[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TRISx[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |
Bits 31:16 – ALTTRISx[15:0] Output Enable for PORTx bits
| Value | Description |
|---|---|
1 |
LATx[n] is not driven on the PORTx[n] pin |
0 |
LATx[n] is driven on the PORTx[n] pin |
Bits 15:0 – TRISx[15:0] Output Enable for PORTx bits
| Value | Description |
|---|---|
1 | LATx[n] is not driven on the PORTx[n] pin |
0 | LATx[n] is driven on the PORTx[n] pin |