14.3.54 IOIM x Status Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | IOIMxSTAT |
| Offset: | 0x1E98, 0x1EA4, 0x1EB0, 0x1EBC, 0x1EC8, 0x1ED4, 0x1EE0, 0x1EEC, 0x1EF8, 0x1F04, 0x1F10, 0x1F1C, 0x1F28, 0x1F34, 0x1F40, 0x1F4C |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ERRCNT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FFEDGE | FREDGE | RFEDGE | RREDGE | OVF | ERR | OK | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 15:8 – ERRCNT[7:0] Error Counter bits
Bit 7 – FFEDGE Feedback Falling Edge Status bit
| Value | Description |
|---|---|
1 | At least one fall transition has been detected on the feedback input |
0 | No reference fall edge has occurred |
Bit 6 – FREDGE Feedback Rising Edge Status bit
| Value | Description |
|---|---|
1 | At least one rise transition has been detected |
0 | No reference rise edge has occurred on the feedback input |
Bit 5 – RFEDGE Reference Falling Edge Status bit
| Value | Description |
|---|---|
1 | At least one fall transition has been detected on the reference input |
0 | No reference fall transition has occurred |
Bit 4 – RREDGE Reference Rise Edge Status bit
| Value | Description |
|---|---|
1 | At least one rise transition has been detected on the reference input |
0 | No reference fall transition has occurred |
Bit 2 – OVF Overflow bit
| Value | Description |
|---|---|
1 | Error counter has overflowed since the last time it was cleared |
0 | Error counter has not overflowed |
Bit 1 – ERR Error bit
| Value | Description |
|---|---|
1 | At least one mismatch has occurred between the reference and feedback inputs |
0 | No mismatches have occurred |
Bit 0 – OK OK bit
| Value | Description |
|---|---|
1 | At least one transition has been detected on the reference input with no mismatch |
0 | No transitions detected on the reference input |