14.3.4 Interrupt Change Notification Status for CNSTATx Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | CNSTATx |
| Offset: | 0x020C, 0x0220, 0x0234, 0x0248 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CNSTATx[15:8] | |||||||||
| Access | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CNSTATx[7:0] | |||||||||
| Access | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CNSTATx[15:8] | |||||||||
| Access | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CNSTATx[7:0] | |||||||||
| Access | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:16 – CNSTATx[15:0] Interrupt Change Notification Status for PORTx bits
When CNSTYLE (CNCONx[11]) = 0:
| Value | Description |
|---|---|
1 |
Change occurred on PORTx[n] since last read of PORTx[n] |
0 |
Change did not occur on PORTx[n] since last read of PORTx[n] |
Bits 15:0 – CNSTATx[15:0] Interrupt Change Notification Status for PORTx bits
When CNSTYLE (CNCONx[11]) = 0:
| Value | Description |
|---|---|
1 | Change occurred on PORTx[n] since last read of PORTx[n] |
0 | Change did not occur on PORTx[n] since last read of PORTx[n] |