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5
Libero IDE
5.34
Project Manager Tcl Commands
5.34.112
backannotate
5.34.112.16
Example
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1
FlashROM, Analog System Builder, and Flash Memory System Builder
2
Analog System Builder, FlashROM and Flash Memory System Builder
3
ChipEditor
4
Designer Documentation Catalog
5
Libero IDE
5.1
What's New in Libero IDE v9.1
5.2
Supported Families
5.3
Project Management
5.4
Project Files
5.5
Project Options
5.6
Settings
5.7
Preferences
5.8
Project Manager Interface
5.9
Designing with Designer Block Components
5.10
Creating a Designer Block Component in Libero IDE
5.11
Creating a Designer Block Component in Designer
5.12
Instantiating a Designer Block Component in Designer
5.13
SmartDesign
5.14
Getting Started with SmartDesign
5.15
SmartDesign User Interface
5.16
Canvas View
5.17
Grid
5.18
Instance-Instance View
5.19
Schematic View
5.20
Creating a SmartDesign
5.21
Connecting Instances
5.22
Bus Interfaces
5.23
Incremental Design
5.24
Reference
5.25
Welcome to Designer
5.26
Device Selection
5.27
Design Constraints
5.28
Families Supported
5.29
Entering Constraints
5.30
Running Layout
5.31
Device Programming
5.32
Generating Programming Files
5.33
TCL Command Reference
5.34
Project Manager Tcl Commands
5.34.1
Arguments
5.34.2
Supported Families
5.34.3
Exceptions
5.34.4
Example
5.34.5
Arguments
5.34.6
Supported Families
5.34.7
Exceptions
5.34.8
Example
5.34.9
Arguments
5.34.10
Supported Families
5.34.11
Exceptions
5.34.12
Example
5.34.13
Arguments
5.34.14
Supported Families
5.34.15
Exceptions
5.34.16
Example
5.34.17
Arguments
5.34.18
Supported Families
5.34.19
Exceptions
5.34.20
Example
5.34.21
Arguments
5.34.22
Supported Families
5.34.23
Exceptions
5.34.24
Example
5.34.25
Arguments
5.34.26
Supported Families
5.34.27
Exceptions
5.34.28
Example
5.34.29
Arguments
5.34.30
Supported Families
5.34.31
Exceptions
5.34.32
Example
5.34.33
Arguments
5.34.34
Supported Families
5.34.35
Exceptions
5.34.36
Example
5.34.37
Arguments
5.34.38
Supported Families
5.34.39
Exceptions
5.34.40
Example
5.34.41
Arguments
5.34.42
Supported Families
5.34.43
Exceptions
5.34.44
Example
5.34.45
Arguments
5.34.46
Supported Families
5.34.47
Exceptions
5.34.48
Example
5.34.49
Arguments
5.34.50
Supported Families
5.34.51
Exceptions
5.34.52
Example
5.34.53
Arguments
5.34.54
Supported Families
5.34.55
Exceptions
5.34.56
Example
5.34.57
Arguments
5.34.58
Supported Families
5.34.59
Exceptions
5.34.60
Example
5.34.61
Arguments
5.34.62
Supported Families
5.34.63
Exceptions
5.34.64
Example
5.34.65
Arguments
5.34.66
Supported Families
5.34.67
Exceptions
5.34.68
Example
5.34.69
Arguments
5.34.70
Supported Families
5.34.71
Exceptions
5.34.72
Example
5.34.73
Arguments
5.34.74
Supported Families
5.34.75
Exceptions
5.34.76
Example
5.34.77
Arguments
5.34.78
Supported Families
5.34.79
Exceptions
5.34.80
Example
5.34.81
Arguments
5.34.82
Supported Families
5.34.83
Exceptions
5.34.84
Example
5.34.85
Arguments
5.34.86
Supported Families
5.34.87
Exceptions
5.34.88
Example
5.34.89
Arguments
5.34.90
Supported Families
5.34.91
Exceptions
5.34.92
Example
5.34.93
Arguments
5.34.94
Supported Families
5.34.95
Exceptions
5.34.96
Example
5.34.97
Arguments
5.34.98
Arguments
5.34.99
Supported Families
5.34.100
Exceptions
5.34.101
Example
5.34.102
Arguments
5.34.103
Supported Families
5.34.104
Exceptions
5.34.105
refresh
5.34.106
set_root
5.34.107
synplify
5.34.108
_pro
5.34.109
unlink
5.34.110
About Designer Tcl commands
5.34.111
Tcl command documentation conventions
5.34.112
backannotate
5.34.112.1
Arguments
5.34.112.2
Supported Families
5.34.112.3
Exceptions
5.34.112.4
Examples
5.34.112.5
Arguments
5.34.112.6
Supported Families
5.34.112.7
Exceptions
5.34.112.8
Examples
5.34.112.9
Arguments
5.34.112.10
Supported Families
5.34.112.11
Description
5.34.112.12
Example
5.34.112.13
Arguments
5.34.112.14
Supported Families
5.34.112.15
Exceptions
5.34.112.16
Example
5.34.113
compile
5.34.114
export
5.34.115
export (IGLOO, ProASIC3, SmartFusion, and Fusion)
5.34.116
ProASIC PLUSProASIC PLUSexport (ProASIC PLUS, ProASIC, Axcelerator, MX, eX, and SX/SX-A)
5.34.117
export (Designer Block support for IGLOO, Fusion, ProASIC3, Axcelerator, and RTAX families)
5.34.118
layout - IGLOO, ProASIC3, SmartFusion, and Fusion
5.34.119
layout - ProASIC and ProASIC PLUS
5.34.120
layout - Axcelerator
5.34.121
layout - SX-A, eX, and SX
5.34.122
layout - MX, DX, ACT
5.34.123
LOGFILE
5.34.124
report
5.34.125
report (Bottleneck) using SmartTime
5.34.126
report (Cycle Accurate Power Report)
5.34.127
report (Datasheet) using SmartTime
5.34.128
report (Power Scenario)
5.34.129
report (Timing) using SmartTime
5.34.130
report (Timing violations) using SmartTime
5.34.131
Add or Edit profile Dialog Box
5.34.132
Project Manager - Cores Dialog Box (Advanced Download Mode
5.34.133
Catalog Options Dialog Box
5.34.134
CDB File Organization Dialog Box
5.34.135
Change All Links Dialog Box
5.34.136
Configure Flow Dialog Box
5.34.137
Convert Project Dialog Box
5.34.138
Export Profiles Dialog Box
5.34.139
Import Files Dialog Box (Project Manager)
5.34.140
New Project Wizard: Add Files
5.34.141
New Project Wizard: Completing
5.34.142
New Project Wizard: Start
5.34.143
New Project Wizard: Select Device
5.34.144
New Project Wizard: Select Integrated Tools
5.34.145
Open Project Dialog Box
5.34.146
Organize Constraints for Synthesis Dialog Box
5.34.147
Organize Stimulus Dialog Box
5.34.148
Page Setup Dialog Box
5.34.149
Profiles Dialog Box
5.34.150
Save Project As Dialog Box
5.34.151
Script Export Options Dialog Box
5.35
Reference
5.36
Dialog Boxes
5.37
Revision History
5
Microchip FPGA Support
5
Microchip Information
6
Design Constraints for Software
7
Innoveda eProduct Designer Interface Guide - UNIX
8
Innoveda eProduct Designer Interface Guide – Windows
9
FlashPro for Software
10
SmartGen Cores Reference
11
HDL Coding Style
12
Libero IDE Documentation Catalog
13
Libero IDE
14
Antifuse Macro Library Guide for Software
15
MultiView Navigator
16
NetlistViewer (non-MVN)
17
IGLOO, ProASIC3, SmartFusion and Fusion Macro Library for Software
18
ProASIC and ProASIC PLUS Macro Library for Software
19
PinEditor (non-MVN)
20
SmartPower
21
SmartTime
22
Timer
23
VHDL Vital Simulation
24
Verilog Simulation
25
Technical Support
26
About Microchip
5.34.112.16 Example
if { [catch { close_design }] {
Puts “Failed to close design” # Handle Failure
Rev: A
