13.6.18 PWM Generator x Event Register High

Note:

An interrupt is only generated on the rising edge of the PCI Fault active signal.
An interrupt is only generated on the rising edge of the PCI current limit active signal.
An interrupt is only generated on the rising edge of the PCI feed-forward active signal.
An interrupt is only generated on the rising edge of the PCI Sync active signal.

Name:	PGxEVTH
Offset:	0x336, 0x36C, 0x3A2, 0x3D8, 0x444, 0x4B0


Bit	15	14	13	12	11	10	9	8
	FLTIEN	CLIEN	FFIEN	SIEN			IEVTSEL[1:0]
Access	R/W	R/W	R/W	R/W			R/W	R/W
Reset	0	0	0	0			0	0


Bit	7	6	5	4	3	2	1	0
	ADTR2EN3	ADTR2EN2	ADTR2EN1	ADTR1OFS[4:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 15 – FLTIEN PCI Fault Interrupt Enable bit⁽¹⁾

Value	Description
`1`	Fault interrupt is enabled
`0`	Fault interrupt is disabled

Bit 14 – CLIEN PCI Current-Limit Interrupt Enable bit⁽²⁾

Value	Description
`1`	Current limit interrupt is enabled
`0`	Current limit interrupt is disabled

Bit 13 – FFIEN PCI Feed-Forward Interrupt Enable bit⁽³⁾

Value	Description
`1`	Feed-forward interrupt is enabled
`0`	Feed-forward interrupt is disabled

Bit 12 – SIEN PCI Sync Interrupt Enable bit⁽⁴⁾

Value	Description
`1`	Sync interrupt is enabled
`0`	Sync interrupt is disabled

Bits 9:8 – IEVTSEL[1:0] Interrupt Event Selection bits

Value	Description
`11`	Time base interrupts are disabled (Sync, Fault, current limit and feed-forward events can be independently enabled)
`10`	Interrupts CPU at ADC Trigger 1 event
`01`	Interrupts CPU at TRIGA compare event
`00`	Interrupts CPU at EOC

Bit 7 – ADTR2EN3 ADC Trigger 2 Source is PGxTRIGC Compare Event Enable bit

Value	Description
`1`	PGxTRIGC register compare event is enabled as trigger source for ADC Trigger 2
`0`	PGxTRIGC register compare event is disabled as trigger source for ADC Trigger 2

Bit 6 – ADTR2EN2 ADC Trigger 2 Source is PGxTRIGB Compare Event Enable bit

Value	Description
`1`	PGxTRIGB register compare event is enabled as trigger source for ADC Trigger 2
`0`	PGxTRIGB register compare event is disabled as trigger source for ADC Trigger 2

Bit 5 – ADTR2EN1 ADC Trigger 2 Source is PGxTRIGA Compare Event Enable bit

Value	Description
`1`	PGxTRIGA register compare event is enabled as trigger source for ADC Trigger 2
`0`	PGxTRIGA register compare event is disabled as trigger source for ADC Trigger 2

Bits 4:0 – ADTR1OFS[4:0] ADC Trigger 1 Offset Selection bits

Value	Description
`11111`	Offset by 31 trigger events
. . .
`00010`	Offset by 2 trigger events
`00001`	Offset by 1 trigger event
`00000`	No offset

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